148 Cadence Virtuoso Jobs - Page 3

The ideal candidate for this position should have 1-2 years of experience in AMS design verification. You will be responsible for developing Verilog/VerilogA/VerilogAMS models for signal and power management modules to support top-level verification. Experience in full chip DV would be an added advantage. You will contribute to the development of the Full-Chip AMS-DV plan and own significant pieces of this verification process. It is essential to have the ability to drive best practices in the field of AMS-DV. In this role, you will work independently to identify bugs and resolve them formally with cross-functional teams. An understanding of analog power IPs will be beneficial as it can help...

Location: Bangalore, India Experience: 2+ Years Notice Period: Immediate to 1 Month Preferred About Genisup India Private Limited Genisup India Private Limited is a leading semiconductor and system design company headquartered in Bangalore. We specialize in Foundational IP Fabless Design, Semiconductor & Product Engineering, and IoT solutions. Our client portfolio includes top-tier companies such as NXP, Qualcomm, and Analog Devices. We are committed to delivering innovative solutions and technical excellence in the semiconductor industry. Role Overview We are looking for an experienced Senior Analog Layout Design Engineer with strong expertise in standard cell layout design to join our team...

Analog Design Engineer with exposure to ADC/DAC/ PLL designs . Job Description In your new role you will: Be a part of the SRSS team in India, where you will: Own and contribute towards designing of Analog I/P . Design and test analog electronic circuits, including sensor interfaces, data converters, multiplexers, active and passive filters, and power distribution systems. Simulate analog or mixed-signal circuits to ensure that performance, noise, timing, and power requirements are satisfied including worst-case and/or statistical design verification and de-rating analysis. Perform the block level and transistor level layout design and optimization of sensor array readout circuits using CAD ...

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regr...

As an Analog Layout Engineer at AISemiCon, you will play a critical role in the design and development of high-performance analog and mixed-signal integrated circuits (ICs). Your main responsibility will be to create layout designs for analog blocks and ensure their adherence to design rules, specifications, and performance targets. You will collaborate closely with cross-functional teams, including circuit designers, verification engineers, and process engineers, to achieve optimal layout implementation. We are seeking individuals with a strong passion for analog layout, deep expertise in IC design, and a keen eye for detail. The key responsibilities for this role include, but are not limit...

The detailed JD is given below Requirements : - B.Tech/M.Tech with 5+ Years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDN s. Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal building blocks such as Power Management, PLL/Synthesizers, ADC, DAC, bandgap references, oscillators/clocking circuits, Phase Interpolators, SerDes etc. and related digital control and signal processing. Demonstrated experience of verification plan development, UVM verification environment d...

You will be responsible for Analog Layout tasks with a focus on AMS/IO Memory, Full-custom circuit layout/verification, and RC extraction. Your role will involve working with lower nodes from TSMC, specifically focusing on ESD Blocks. As an Experienced Layout Engineer at ACL Digital, you should hold a Bachelor's or Master's Degree with a minimum of 4 years of Analog Layout experience. In this position, you will need to demonstrate leadership skills acquired over at least 3 years, including hiring, nurturing talent, leading project execution, and managing clients and stakeholders effectively. Your excellent communication skills will be crucial, along with a hands-on approach to your work. An ...

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and integrating them into full-chip designs. Your expertise in lower technology nodes, physical layout techniques, and verification processes will be crucial for success in this role. You will collaborate with circuit design teams to optimize layout quality and performance, ensuring that layouts meet design matching and parasitic constraints. Working with advanced nodes like 7nm, 16nm, and 28nm, you will play a key role in advancing the company's cutting-edge projects. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Pe...

B.Tech/M.Tech with 5+ Years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDN’s

We are seeking a highly skilled Senior Analog Design Engineer with 6+ years of experience in designing, simulating, and validating analog and mixed-signal circuits. The ideal candidate should have hands-on expertise across the full custom design flow, from specification to silicon validation. Key Responsibilities: Design and develop analog/mixed-signal IPs such as ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps, etc. Perform schematic entry, simulations (pre-layout/post-layout), and layout supervision. Drive transistor-level design using industry-standard tools (Cadence/Synopsys). Lead block-level design reviews, documentation, and verification. Collaborate with layout, digital, and validation tea...

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides f...

As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Additionally, exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Proficiency in EDA tools is essential for ...

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon e...

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred...

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate ...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from de...

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shi...

Senior Engineer - Standard Cell Layout Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12161 Remote Eligible No Date Posted ...

As a Layout Design Engineer at Micron Technology, you will play a crucial role in developing critical analog, mixed-signal, and custom digital blocks. Your responsibilities will include designing and developing layout designs, performing layout verification such as LVS/DRC/Antenna, conducting quality checks, and providing support documentation. It will be your responsibility to ensure timely delivery of block-level layouts with acceptable quality while taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a supportive team player are essential aspects of this role. To be successful in this position, you should have...

As a Layout Design Engineer at Micron Technology, you will be responsible for the design and development of critical analog, mixed-signal, and custom digital blocks. Your role will involve performing layout verification tasks such as LVS/DRC/Antenna checks, ensuring quality, and supporting documentation. It will be crucial for you to deliver block-level layouts on time with acceptable quality, taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a strong team player are essential aspects of this role. To qualify for this position, you should have 2 to 5 years of experience in analog/custom layout design in advance...

Job Requirements Bachelor or master Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high speed layout, e. g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR & Self-heating e...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layo...

Education Graduation in Pharmacy Long Description The person should have knowledge in Manufacturing equipments. He should have exposure in equipment’s such as FBE,Fette/KORSCH M/C & auto coater M/C He should be able to handle equipment trouble shoot in Manufacturing department. He should have exposure in regulatory organization . He must have faced the USFDA ,MHRA & other regulatory audits. He should have the exposure in Caliber QAMS, elog, track wise ,SAP ,WIND ,CDAS & other software. He should have the exposure in process simplification/optimization ,SABA ,elog & SCADA. Competencies Work Experience 3-6 years work experience in Fette compression machine

We are hiring an experienced Analog Layout Engineer to join a high-performance team working on advanced node technologies. This is a great opportunity to work with a global leader in semiconductor technology. Location: Bangalore Experience: 8 10 Years Employment Type: [Contract] Key Responsibilities: Handle block-level and top-level analog layout. Work on matching techniques, layout parasitics, and advanced layout methodologies. Work independently and collaboratively in a cross-functional team. Ensure quality layout delivery meeting DRC, LVS, and reliability checks. Required Skills: Solid understanding of analog layout fundamentals and design methodologies. Proficiency in 28nm, 22nm, and 16f...