238 Cadence Virtuoso Jobs - Page 3

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Characterization Engineer, you will work with a highly innovative and motivated design team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips with huge scale of circuit capability, ultra-high-speed designs, complex functionality which inclu...

Role Overview: As an Analog Layout Engineer at Radiant Semiconductors, you will be responsible for designing and implementing analog layouts for high-performance circuits such as amplifiers, ADCs, DACs, and voltage regulators using TSMC/Samsung 7nm and below nodes. Your role will involve ensuring design compliance by performing design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC). Key Responsibilities: - Design and implement analog layouts for high-performance circuits using TSMC/Samsung 7nm and below nodes - Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) Qualifications Required: - 3 to 8 years of experie...

As a talented Custom TechFile PDK Engineer, your role will involve developing and maintaining custom Tech Files as part of Process Design Kits (PDKs) for advanced semiconductor technologies. You will be responsible for creating, validating, and optimizing custom Tech Files to facilitate efficient and accurate custom layout design. Collaboration with design teams, EDA tool vendors, and process engineers will be essential to ensure the seamless integration of PDKs into design flows. **Key Responsibilities:** - Develop and maintain custom Techfile and their qualification. - Ensure compatibility of PDKs with industry-standard EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, and Ment...

We’re hiring Analog Layout Engineers (3–7 years) with hands-on experience in lower technology nodes, layout design, and DRC/LVS verification. Location: Hyderabad. Immediate joiners preferred.

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shi...

Title: Senior Manager, Silicon Photonics Reference Design About GLOBALFOUNDRIES GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Job Description We are seeking an experienced Senior Manager to lead our Reference Design team for GF's industry-leading Fotonix platform. This position involves advancing S...

Designation: Principal AMS Layout Leader (Global Product Solution Opportunity) Exp Range: 15-25 Yrs Location: Hyderabad Job Description A layout technical expert taking chip top ownership of analog-on-top ASIC developments. Hands-on technical contributor, able to take chiptop ownership including tape-out procedures. A teamplayer, able to collaborate within a global layout team and cross-discipline stakeholders. Required experience: 15+ years of experience Experience with nodes in the range of 22nm-40nm-180nm is a must. Experience with BCD technologies is a must. Proven track record of owning chip top layout. Must be able to independently go through required tape-out procedures and take corre...

Analog circuits, Analog models Exp in Cadence Virtuoso, Cadence Spectre/TISpice, Verilog-AMS/System Verilog. AMS simulations, digital RTL, analog schematics. Proficiency in scripting languages and utilities, including Python, Perl, etc.

You will be working as an AMS Verification Engineer with a focus on Analog-Mixed Signal designs. Your role will involve developing and executing verification plans, performing behavioral modeling, and ensuring the functionality and performance of various AMS circuits like PLLs, ADCs, DACs, and LDOs. - Develop AMS verification plans based on design specifications. - Perform mixed-signal co-simulation using tools such as Cadence Virtuoso, Spectre, and Xcelium. - Create Verilog-A/Verilog-AMS behavioral models for analog/mixed-signal blocks. - Develop testbenches using UVM-AMS or other methodologies for mixed-signal verification. - Define and execute functional, performance, and corner case veri...

Company Description Thalia is a venture-funded technology business with facilities in Cwmbran, United Kingdom; Hyderabad, India; and Cologne, Germany. The company provides analog and mixed signal design solutions for integrated circuit (IC) manufacturers and IP companies utilizing unique design automation technology and strong value-added services capabilities. With support from investors like Mercia Fund Management and Finance Wales, along with grants from Innovate UK and The Welsh Government, Thalia enables customers to migrate designs, generate portfolios, and develop faster IPs, achieving reduced design cycles, lower costs, and shorter time to market. Thalia has successfully delivered nu...

Hi All, Title : Analog Layout Engineer Exp Level:3+ yrs Location: Bangalore Job Description: Design and development of full custom analog/mixed-signal layout at block and top level. Strong expertise in analog layout techniques for circuits such as ADC, DAC, PLL, LDO, Bandgap, etc. Hands-on experience with layout tools like Cadence Virtuoso, Calibre, and Mentor tools. Ensure layout meets DRC, LVS, ERC, Antenna, and other physical verification requirements. Work closely with circuit design engineers to plan, review, and optimize layout. Experience in advanced process nodes (e.g., 7nm, 5nm, 3nm) preferred. Understanding of EMIR, ESD, and reliability requirements Proficient in hierarchical and f...

Role : (in 100 to 150 words) Participate in consulting assignments, identify and mentor Six Sigma and Lean projects, and drive process improvement activities and business transformation in the customer service vertical. Reports into : (RM Designation) GM QPE Job Responsibilities : (Must have) (min 8 pointers & max 12) Participate in PEx. consulting assignments Identify and mentor Six Sigma and Lean projects Conduct Value Stream Mapping/Process Mapping Ensure compliance with ISO 9001/ 27001 standards Drive process improvement activities Lead business transformation initiatives Promote and drive the Six Sigma culture and initiatives Mentor MBB , BB , Green Belt trainees Recommend new/improveme...

As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. Your role will require you to have a strong background in custom layout for high-speed IPs like PLLs, SERDES, clock buffers, and data paths. Key Responsibilities: - Hands-on experience in custom layout for high-speed IPs including PLLs, SERDES, clock buffers, and data paths - Proficiency in tools like Cadence Virtuoso, Calibre DRC/LVS, and PEX flows - Demonstrated track record of delivering clean layouts with successful DRC/LVS/EM/IR sign-offs through multiple tapeouts - Expertise in lay...

With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification, and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To: - Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. - Proactively identify problem areas for improvement, propose, and develop innovative solutions. - Develop...

We are looking for a skilled SAP DRC Consultant with 19 years of experience to join our team at Forward Eye Technologies. The ideal candidate will have a strong background in SAP DRC and be able to work effectively in a fast-paced environment. Roles and Responsibility Collaborate with cross-functional teams to design and implement SAP DRC solutions. Provide technical expertise and support for SAP DRC projects. Develop and maintain documentation for SAP DRC implementations. Troubleshoot and resolve complex technical issues related to SAP DRC. Conduct training sessions for end-users on SAP DRC functionality. Work closely with stakeholders to understand business requirements and develop solutio...

BE/B.Tech /ME/M.Tech 4 years to 8 years He/She should be able to act as focal point with customers, work and lead a team of 3-4 customlayoutengineers onanaloglayout, physical verification, maintaining PDKs, ealuating them. The candidates should have a strong expertise in some criticallayouts such as PLL, DLL, LNA, VGA, ADC, LDO. He/She should be able to adapt to new technologies/tools/flows pretty quickly. Expertise in CustomLayoutStandard Cells, I/O or specialanalogdesigns such as RF transceivers, LNA, VGA, PLL, DLL, LDO, Bandgap, VCO, ADC,DAC. StrongLayoutDesign Concepts. Experience in Pcell development, maintaining and modifying PDKs. Experience inLayoutDesign tools such as Virtuoso, Virt...

As an Analog Layout Designer at UST, you will be responsible for independently working on block level and chip level Analog layout design while collaborating with circuit designers and project leads. Your role will require a minimum of 3+ years of hands-on experience in Analog layout, specifically focusing on custom layout design for DAC, ADC, Band gap, Regulators, LDOs, etc. Additionally, knowledge of finfet or exposure to technology at 28nm or below will be advantageous. You should possess a thorough understanding of IC fabrication and reliability issues and be well-versed in tools like Cadence-Virtuoso, PVS, ASSURA, and Calibre. Strong written and verbal communication skills are essential...

As an experienced Analog Layout design engineer, you are expected to be innovative, collaborative, meticulous, and curious. Key Responsibilities: - Layout of basic digital and analog building blocks using analog transistor level components. - Layout of analog macros, power pads, and input/output pads using the above blocks. - Working closely with Analog designers in floorplanning; power grid and signal flow planning. - Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up, and PERC ESD. - Creation of blackbox models for other groups in the design flow. Preferred Experience: - Must have detailed knowledge of CMOS circuit theory. - Must have the ability to communicat...

As an AMS Design, Verification and Layout professional with 4+ years of experience in the Semiconductor domain, your role will involve: - Designing analog and mixed-signal circuits like amplifiers, data converters, PLLs, and regulators. You will conduct detailed transistor-level simulations including DC, AC, transient, PVT, and Monte Carlo. - Developing and maintaining behavioral models using Verilog-A/AMS. You will also create comprehensive testbenches for mixed-signal co-simulation with digital blocks. - Executing block-level and top-level verification, encompassing functional, corner-case, noise, and signoff simulations to ensure design adherence to specifications in all scenarios. - Crea...

As a candidate for the position, you should have a Bachelor's or Master's Degree with 3-10 years of Analog Layout experience. It is essential to possess a good understanding of advanced semiconductor technology process and device physics. Your role will involve full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high-speed layout, e.g., PLL, IO, RF, PMIC, OSC, DC-DC converter, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD. You should be familiar with the Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc.). Experience in advanced technology nod...

You have experience in Mixed-Signal layouts and must have worked with TSMC 7nm / 5nm FINFET technology. It is also preferred that you have knowledge of keywords like 22FDX / 12FDX / FDSOI. Your responsibilities will include working on various Mixed-Signal layout blocks such as: - High-speed SerDes like Transmitter(Tx), Receiver(Rx), PLL, USR, LNA, etc. - Analog-to-Digital Converters (ADCs) such as Successive Approximation (SAR) ADC, Delta-sigma () ADC, Dual Slope ADC, Pipelined ADC, Flash ADC. - Digital-to Analog Converters (DACs) including Weighted Resistor DAC, R-2R Ladder DAC. - GPIO, XTAL, Auxiliary cells. - High-speed IOs like DDR2/3/4, MIPI, SATA, USB, LVDS, etc. You should have hands-...

We are looking for a skilled SAP DRC Engineer with 7 to 12 years of experience. The ideal candidate will have expertise in the SAP DRC module and BTP of SAP, SD, FI, E-Doc Cockpit, and project management skills. This position is available in PAN India, including Bangalore, Hyderabad, Chennai, Noida, Pune, and Gurgaon. Roles and Responsibility Design and implement SAP DRC solutions to meet business requirements. Collaborate with cross-functional teams to ensure seamless integration of SAP DRC with other modules. Develop and maintain documentation for SAP DRC projects. Provide training and support to end-users on SAP DRC functionality. Troubleshoot and resolve technical issues related to SAP D...

AMS Verification Job Location: Bangalore Job Description: 4-6 yrs of exp in mixed-signal verification of chip Experience with mixed signal / co-simulation (analog, digital) verification methodologies Experience writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews Experience developing behavioral models for analog IPs in WREAL, Verilog-AMS Understand and debug digital RTL and analog schematics Working knowledge of state-of-the-art EDA tools: Cadence Virtuoso, Cadence Incisiv/Xcelium, Cadence Vmanager Strong background in verification languages and methodologies (e.g. Verilog, SystemVerilog, UVM, SVA). E...

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualificatio...