Lead Engineer - Analog Design

3 - 10 years

0 Lacs

Posted:21 hours ago| Platform: Shine logo

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Work Mode

On-site

Job Type

Full Time

Job Description

As a candidate for the position, you should have a Bachelor's or Master's Degree with 3-10 years of Analog Layout experience. It is essential to possess a good understanding of advanced semiconductor technology process and device physics. Your role will involve full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high-speed layout, e.g., PLL, IO, RF, PMIC, OSC, DC-DC converter, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD. You should be familiar with the Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc.). Experience in advanced technology nodes under 16nm/14nm/7nm is required, and knowledge of 5nm/3nm will be an added advantage. Expertise in Totem EMIR & Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC, etc.) is a must. A good understanding of layout fundamentals such as Matching, EM, ESD, Latch up, coupling, crosstalk, etc., is necessary. You should also have experience in top-level floorplan, hierarchical layout methodologies. Programming skills in "SKILL" automation and a circuit design background are considered a plus. Good communication skills and willingness to work with a global team are essential for this role. Your ability to learn quickly, be self-motivated, and work in diverse areas in a flexible and dynamic environment are key attributes required for this position. Please note that the provided job description includes the same details under the section "Work Experience" as mentioned earlier in the job requirements.,

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