44 Esd Jobs

To prepare bids for Automation (Control) Systems for Pharmaceutical, Innovation and Digitalization Solution’s for Chemical API and Bio-process Industry Vertical. Having basic knowledge for proposal making for Automation System & Instrumentation. This role is an important & valuable link in the Acquisition phase & overall project lifecycle. The role involves preparation of comprehensive customer proposal in line with customer’s requirements /specifications & Siemens guidelines. It is important to prepare the best fit proposal & contribute towards becoming preferred as well as competitive in order to secure the order. Once the project is bagged, It is required to support for smooth transition of Order booking, Order acceptance and Handover to Project Management. Scope of Working in offer making:- Read the enquiry Specifications provided by customer and understand it so as to select the applicable Automation systems, Panels, Bought outs etc. and Quantify them. Design Automation system with selection of CPU, I/O cards, Panel, Networking, software etc Preparing system Architecture in Visio. Preparation of costing. Aligning with other internal stake holders for pricing / approvals viz Purchase team, Engg, team, Finance team, Legal team etc Preparing Technical Compliance sheet, Costing and Offer with applicable documentation in accordance with Enquiry Specifications. Align with vendors for availing backup offers of bought out items and co-ordinate with SCM for negotiated best price from vendor to avail best discounted prices. Preparing Technical Compliance sheet, Costing and Offer with applicable documentation in accordance with Enquiry Specifications. Align with Sales Manager and customer for technical compliance, optimization and best fit solution from House of Siemens. Evaluate the Technical, Commercial risk with applicable impact and its mitigation measures Prepare project execution timelines in accordance with customer requirement and measures to overcome delays wrt HW / BO / Engg and Commissioning. Follow Proposal Management Quality procedures and support for Quality ISO audits Pre-Requisite:- Having Diploma/ Degree in Instrumentation or Electronics with 3 - 5 years of experience. Experience and knowledge in Instrumentation and control (DCS/PLC/ESD) Knowledge of DCS, ESD & PLC and Zone classification and Communication protocols, Digitalization. Should have basic domain knowledge for Pharmaceutical Industry viz. Chemical API, Life science industry, Tank farm automation etc. Good in speaking and Writing in English and communication. Knowledge of Excel and Word. Knowledge of tender documentation and bid preparation. Strong Communication and Interactive. Disciplined This role is based at Siemens Ltd. Kalwa (Navi Mumbai).

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 8 to 12 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic /PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: As a Staff/Senior Staff SoC Physical Verification Engineer, you will be responsible for leading and executing full-chip and block-level physical verification (PV) for advanced SoC designs. You will collaborate with cross-functional teams to ensure design integrity, manufacturability, and compliance with foundry rules across multiple technology nodes (e.g., 7nm, 5nm, 3nm). Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Key Responsibilities: Own and drive physical verification (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical Design (PD), RTL, and CAD teams to resolve PV issues and ensure sign-off quality. Analyze and debug PV violations using tools like Calibre, ICV, and IC Validator. Work on ESD routing, bump/RDL planning, and padring integration. Develop and refine PV flows and methodologies in collaboration with CAD teams. Mentor junior engineers and lead PV closure for complex SoC programs. Interface with foundries for rule deck updates and tapeout readiness. Required Skills & Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or related field. 7"“14 years of hands-on experience in SoC physical verification. Strong expertise in Calibre, ICV, ICC2, Fusion Compiler, and Innovus. Deep understanding of DRC, LVS, ERC, PERC, Antenna, and density checks. Experience with advanced nodes (7nm and below) and FinFET technologies. Familiarity with scripting (TCL, Perl, Python) for automation and debugging. Exposure to ESD, latch-up, IR drop, and EM analysis. Excellent problem-solving, communication, and leadership skills. Preferred Qualifications: Experience with Intel, TSMC, or Samsung foundry rule decks. Knowledge of RTL-to-GDSII flow and ECO implementation. Prior experience in customer-facing or cross-site collaboration roles.

Role & responsibilities Job description We are seeking a detail-oriented hardware design engineer for design and development activities of our product line (SMPS/Chargers etc). The following would be the main responsibilities: 1. Hands on Experience on, SMPS & Chargers. 2. Knowledge of Power electronics. 3. Hands on Experience in circuit design, simulation, filter design, schematic & Layout, Micorcontroller based designs, UART/RS232/RS485/CAN/ LIN communication, DFMEA. 5. Hands on experience in validation jig designing using arduino. 6. Knowledge of transformers and inductors calculation, Thermal calculations and components selections/design, BOM preparation. 7. Knowledge of power switching topologies. like fkyback, LLC, PFc topologies. 8. Special Preference who has experience in, Inverters design & charger designing etc.. 9. Hands on Experience in Design Verification and Product Validation. 10. Good understanding on EMI/EMC, ESD testing. 11. Resolve issues in mass production of the design and manufacturing assembly line. 12. Go-Getter, Self Learner, Positive Attitude Preferred candidate profile Only Male Candidate, Willing to work in 6 days working setup. Perks and benefits Insurance,Bouns ,PF

Job Description: Electronics Test & Debug Engineer Position Overview: We are seeking a highly skilled Electronics Test & Repair Engineer . The ideal candidate will have hands-on experience with testing, troubleshooting and repairing electronic components, along with expertise in signal analysis and industry-standard testing tools. Key Responsibilities: Knowledge of ESD & 6S Understanding the testing log Load testing of power supply Block diagram knowledge of SMPS System Testing tools knowledge i.e. Multi meter, CRO Understanding of Schematic, Signal flow, RBOM and board view Helping in Troubleshooting guidelines preparation knowledge of Electronics PCBA, BTS & BTS card (i.e. Control card, Channel Card, Duplexer, RRH, Microcell, MMU), DWDM Knowledge of Technology (2G, 3G, 4G & 5G) Knowledge of signal Communication (modulation, demodulation, Uplink Frequency, Downlink Frequency, TX, Rx, VSWR, SNR, etc.) Testing tools knowledge i.e. Multi meter, CRO, Signal Generator, Frequency Generator, Spectrum Analyser, Power Meter, Frequency counter, RACAL, etc. Repair & Debug with JTAG S/W, FTJ loader, Flash programmer. Qualifications: Diploma/Bachelors degree in Electronics, Telecommunications, Electrical Engineering , or a related field. 2+ years of experience in electronics testing, debugging, and troubleshooting . Ability to work independently and collaborate within a technical team.

Lead design of analog/mixed-signal ICs (ADC/DAC, PLL, LDO/DCDC, IO Drivers). Oversee verification, layout compliance, cross-functional collaboration, and product support. Utilize EDA tools for design, simulation, and debugging. Required Candidate profile Experienced analog/mixed-signal IC designer (8+ yrs), adept in variation-aware design, verification, debugging, and product support. Strong in cross-functional collaboration. Masters in VLSI or ECE

ROLES & RESPONSIBILITIES: Basic & Detailed Engineering & Design of Instrumentation & Control Systems for EPC Projects in the field of Oil & Gas Sector (Offshore / Onshore), Petrochemicals, Hydrocarbon, Power Plants, Metals and Mining & Process Industries. Candidate should be able to understand P&ID, review Project Scope of Work and develop Instrumentation & Control systems related detailed engineering drawings and documents assisting Draftsman. Should have knowledge of Field Instruments, Transmitters & Gauges, Control Valves, On-Off Actuated Valves, PSV's, PLCs, DCS system, ESD Systems, F&G Systems, Fire & Gas Detectors and Devices, Preparation of MR/RFQ, TBE, Offer Evaluation, PR & Vendor Document Review (VDR). Should have knowledge of development of System Architecture, Instrument Index, Instrument Data sheets, Package Specifications, Cable Block Diagrams, Hook-up Drawings, Cable Route Layouts and Schedules, Logic Diagrams, Bill of Material, MTO etc.

Job Information Job Opening ID ZR_1777_JOB Date Opened 24/03/2023 Industry Technology Job Type Work Experience 6-10 years Job Title Electronics Engineer City Gurgaon Province Haryana Country India Postal Code 201303 Number of Positions 1 Should have experience on Mixed Signal Design, Analog Circuit Design and Digital Circuit Design Should have experience in working on complete Product Development Life Cycle Should have a strong understanding of Signal and power Integrity phenomena and relevant tools. Should have knowledge of working on micro controllers, microprocessors and FPGAs from various industry manufacturers like TI, STM, Qualcomm, Xilinx, Lattice and others. Should have knowledge of communication protocols like SPI, I2C, USB, UART, CAN, Ethernet, Wi-Fi, RS485 a few to mention. Should possess excellent knowledge of various power regulators like Switching and LDOs. Should have experience of Schematic Design in Altium and Orcad Should have reviewed the layout designs and guided PCB designers for an effective component placement and routing for various designs. Should have worked on Multi-layer board design with minimum 6 layers. Understanding of the layer stack-up definition and its understanding is desired. Should have knowledge of using various electronic tools and instruments like Oscilloscopes, multi meters and others. Should have excellent debugging skills with analytical reasoning. Should have experience in making the designs meet various compliance standards related to safety, ESD, EMI/EMC. Excellent interpersonal, written and verbal communications skills; flexible, self-directed and able to work in a team environment. Knowledge of Change/Configuration Management and ECN processes is a Plus Should possess excellent knowledge of various power regulators like Switching and LDOs. AC to DC Power Supply Design and debugging Should have strong knowledge in working on various motors like BLDC, stepper, etc. Should have strong knowledge of working on Encoders, motor drive........Bold are mandatory skills. check(event) ; career-website-detail-template-2 => apply(record.id,meta)" mousedown="lyte-button => check(event)" final-style="background-color:#2B39C2;border-color:#2B39C2;color:white;" final-class="lyte-button lyteBackgroundColorBtn lyteSuccess" lyte-rendered=""> I'm interested

Key Responsibilities/Deliver: 1.Design and development of Electronics Hardware, & its testing 2.Power supply design SMPS topologies, DC-DC converters, High frequency transformer design. 3.Analog & Digital circuit design, its signal integrity Simulation in Pspice, LTSpice, ModelSI IGBT/MOSFET Gate Drivers design, PWM techniques, Snubber design 4.EMI-EMC Filter Design implementation in electronics circuit design, with compliance of Surge, EFT, ESD, CE,CS RE,RS etc. 5.Heatsink calculations, Components selections like Capacitors, LDOs, Inductors, X,Y Capacitors 6.Knowhow of various IEC, CE, UL, standards 7.PCB layout understanding, review. 8.Knowledge of various communication protocols like RTU, USB, CAN, TCP, Profibus, etc. from hardware design perspective. 9.Knowledge of various reliability testing like, HALT, ALT etc. Functional Competencies: 1.Embedded Hardware Design 2.EMI/EMC standard understanding 3.Simulation skills Desired Overall Skills: 1.Effective communication 2.Team player Individual contributor 3.Creative and open to learn. Schneider Electric aspires to be the most inclusive and caring company in the world, by providing equitable opportunities to everyone, everywhere, and ensuring all employees feel uniquely valued and safe to contribute their best We mirror the diversity of the communities in which we operate and we embrace different as one of our core values. We believe our differences make us stronger as a company and as individuals and we are committed to championing inclusivity in everything we do. This extends to our Candidates and is embedded in our Hiring Practices. You can find out more about our commitment to Diversity, Equity and Inclusion here and our DEI Policy here Schneider Electric is an Equal Opportunity Employer. It is our policy to provide equal employment and advancement opportunities in the areas of recruiting, hiring, training, transferring, and promoting all qualified individuals regardless of race, religion, color, gender, disability, national origin, ancestry, age, military status, sexual orientation, marital status, or any other legally protected characteristic or conduct. Qualifications Education Qualification: BE (Electronics/ Electronics-communication/industrial/) OR BE (Electronics/ Power Electronics)/ MTech (Power Electronics)

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Responsibilities: Pull daily banking for multiple clients Enter deposits into the reconciliation logs Process timely and accurate posting of all payments Post all payments within 24 hours Meet strict posting deadlines to ensure that Payment Posting Manager can complete weekly and monthly reporting requirements Communicate all payer issues to the Payment Posting Manager Understand payer contract with all rules that apply to that specific payer and client Maintain professional and consistent communication with the team and clients to ensure that all needed items are received in a timely manner Identify patterns and trends that indicate a potential issue Other responsibilities as assigned Required Knowledge, Skills, Abilities & Education: Payment posting Experience with accounts receivable Experience with some or all of the following practice management systems: Amkai, SIS/Vision/Advantx, HST, EPIC RESOLUTE, is preferred Knowledge of payer contracts and (EOBs), explanation of benefits Experience working in a clearinghouse Understanding of HIPAA regulations Strong verbal and written skills Great attention to detail to avoid data entry errors Excellent communication skills Strong organizational skills Effective time management A positive, open and friendly attitude to colleagues and clients Superior customer service and professionalism Preferred Knowledge, Skills, Abilities & Education: University certificate in healthcare related field 2+ years Ambulatory Surgical Center coding experience

Responsibilities: * Create detailed layout designs using Virtuoso software. * Perform physical verification through DRC, LVS, ESD checks. * Collaborate with cross-functional teams on floor planning and antenna integration. Annual bonus

What You ll Need: BTech/MTech in Electrical Engineering or related field. Minimum of 3 years of experience with MTech or 5 years with BTech in CMOS circuit design and layout methodology. Strong knowledge of deep submicron process technologies and CMOS processes. Familiarity with JEDEC requirements for DDR interfaces and standards. Experience with ASIC design flow and ESD concepts is an advantage.

Role & responsibilities SPOC for the Supplier Quality Sustenance for the assigned Suppliers or commodity(Electricals, Electronics, EMS etc). Prevention strategies & CAPA for improving supplier SPR (Straight Pass Ratio) and ensuring defect free supplies to Ather Verify Quality, Systems and Process (Electricals, Electronics, EMS etc) in accordance with IATF 16949, ESD 20.20 & IPC requirements at Supplier end on periodic basis. Conduct periodic product audit, Process audit & Layered process audit for all Supplierparts. Work with the SQA & ME to implement preventive process controls to embed Qualityfrom Development to Launch at supplier end. Collaborating with both Suppliers and Ather for the closure especially supplier internalrejections, Tier 2 bugs and bugs reported at Ather. Ensure FPY, OEE of machines as per set target and early communication to Ather Immediate deployment of containment action with cutoff and traceability along witheffective verification of corrective action as per Supplier Quality Requirement Manual Communication to Ather SQA in case of unapproved changes against set PPAP conditions Monitor and validate early production builds to ensure that the Designs, Tools, Jigs and Fixtures are as per Ather requirements Implementation check as per ESD 20.20, product qualification, compliance verification Work closely with the SQA & Manufacturing Engineering, Supplier Management to ensure highest levels of part Quality Work hand in hand with the Ather ME team, as part of the team ensure builds in PCBA & boxbuilds are completed as per the project schedules. Validate testing and process cycle times and yield to meet the TAKT and OEE requirements Execute and monitor the DOEs assigned at foxconn for the box build assembly process mprovements. Follow ups with EMS partner for NPI build readiness Preferred candidate profile Expertise in Supplier Quality Management in the EMS industry. Worked in Electronics Manufacturing Service (EMS) and sound knowledge of SMT , THT & Soldering process along with Bare board (PCB) Working knowledge in understanding assembly instructions & CTQ requirements for PCBs, PCBAs & Box builds. Sound understanding of Gerber & Schematics Expertise in IPC 610A & IPC711 Acceptance level Expertise in PPAP,PFMEA,FTA,8D,SPC ,MSA Understanding and implementation of ESD requirement as per ESD 20.20:21 Good technical, communication skills & Punctuality.

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state of the art tools. You will be collaborating with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges and enabling flows to meets their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and/or modify the existing ones . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualification Minimum 5 years experience in a hands-on PDK role Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna". As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules(DRCs), etc to meet the needs of the design teams You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other Extraction tools Support the design teams with solving their PV challenges to facilitate the IP release and Chip tapeouts Collaborate with tool vendor and foundries for tools and flow improvements Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design Proficiency in one or more of the programming/scripting languages- , Python, Unix, Perl, and TCL. Good communication skills and ability to work collaboratively in a team environment Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: An experienced and passionate Analog Design Engineer with 1-3 years of experience in the field You have a strong background in CMOS processes and deep submicron process technologies You understand the intricacies of CMOS circuit design and layout methodology, and you have a basic understanding of analog/mixed signal circuitry Familiarity with ESD concepts is a plus You are knowledgeable about ASIC design flow and JEDEC requirements for DDR interfaces and standards You excel at executing circuit design tasks with a focus on quality and efficiency Your communication skills are excellent, enabling you to interact effectively with internal development teams, What Youll Be Doing: Designing DDR/HBM Memory Interface I/O circuits and layouts, including GPIO and special I/Os, Collaborating with the DDR/HBM PHY team, package engineers, and system engineers to meet design specifications, Ensuring adherence to best practices in circuit design and layout methodology, Conducting thorough design reviews and contributing to the continuous improvement of design processes, Staying updated with the latest advancements in analog design technologies and methodologies, Documenting design processes and providing support for design validation and testing, The Impact You Will Have: Enhancing the performance and reliability of our analog and mixed-signal circuits, Contributing to the development of high-performance DDR/HBM Memory Interfaces, Supporting the overall success of our chip design and IP integration projects, Driving innovation in analog design methodologies and processes, Ensuring our products meet the highest standards of quality and efficiency, Helping Synopsys maintain its leadership position in the semiconductor industry, What Youll Need: Bachelor's or Master's degree in Electronics or Electrical Engineering, 1-3 years of experience in CMOS processes and deep submicron technologies, Proficiency in CMOS circuit design and layout methodology, Basic understanding of analog/mixed signal circuitry, Familiarity with ASIC design flow and JEDEC requirements for DDR interfaces, Who You Are: A detail-oriented engineer with a passion for analog design, An effective communicator who collaborates well with cross-functional teams, A problem-solver who can analyze and address design challenges efficiently, A continuous learner who stays updated with industry trends and advancements, A team player who contributes to the overall success of the project, The Team Youll Be A Part Of: You'll join a dynamic and innovative team of engineers focused on advancing our analog design capabilities Our team is dedicated to pushing the boundaries of technology and delivering cutting-edge solutions for the semiconductor industry We value collaboration, creativity, and a commitment to excellence in everything we do, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Role & responsibilities Operation and maintenance of SMT machines and equipment and perform Assemble the electromechanical parts as per the work instruction without any defects Perform the given task effectively and follow shop floor best practices Follow 5S & safety practices in shopfloor and maintain the area neat, clean & tidy Handle electronic modules carefully and preserve appropriately Learn and perform new stage operations to become more competent and multiskilled Follow I Own Quality concept to produce quality products Preferred candidate profile General Product Knowledge Basic Knowledge of stage operation & related production Process, Surface Mount Technology assembly process, Hand soldering techniques Ability to learn new tasks quickly & perform efficiently Basic knowledge of ESD, MSD, 5S & other systems Knowledge of materials used for production Knowledge of waste Identification Manual Assembling, soldering & mechanical assembly of components Visual inspection of assemblies Assistance in Preventive maintenance activities Perks and benefits Transportation Available as per Shift timing – Both Pick and drop, additionally for Women employees, House Pick up and drop if shift timing is on 6.00PM to 6.00AM along with escorts Meals – Yes Available As per Shift timing Other benefits : Group Medical Insurance, Group Personal Accident Insurance and Group Term Life Insurance are as per applicable Company Policy. Pre-engagement medical test : Will be organized by Nokia, and all apprentices are required to undergo the same.

Hi, We are hiring for EMI/EMC Test Engineer for Mysore/Mysuru location. Job title: EMC Testing Engineer Work Location: Mysore/Mysuru Division/Department: EMC lab Profile: The EMC Test Engineer is responsible for evaluating, explaining, and completing the test report for intricate customer samples. Follows defined test plans, testing procedures and data sheets for the product under test. Operates and maintains complex test equipment and customer samples. Communicates with customers during setup and operation to ensure proper evaluation. Skills required: strong background in EMC/EMI testing. Knowledge of basic EMC standard like Knowledge of EMC standard like IEC 61000-4 series, IEC 61326, MIL standard, IEC62052-11 series and CISPR series. Knowledge of Emission and Immunity test like Radiated and Conducted emission, ESD, EFT, Surge, Conducted and Radiated Susceptibility test. Exposer of testing in 3M Anechoic chamber. Experience: Minimum 4 years Educational Qualification Required: B.tech/Diploma (E&C/E&E) or M.tech (E&C/E&E). Interested candidates please share your updated resume to nikita.singh@nemko.com or apply here on naukri.com

Experience in Oil and Gas Refinery or petrochemical projects offshore platforms Conversant with Control System DCS/ESD/F&G and Field Instruments Control/Safety Valves, HIPPS, Transmitters, Analyzers, Gauges, communication systems for offshore Required Candidate profile Instrumentation Design Basis Engineering Co-ordination/Fabrication /Loop/ Checking/Commissioning of Instrumentation System Design Documents like Control System Block Diagram/F&G Layouts/Cable Schedule

About The Role As part of the Design Technology Platform Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies, Enablement, Validation and Foundry Certifications of Industry Standard EDA Reliability (EM/IR); ESD Perc tools and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools. Direct reporting of Junior Engineers in the team will be involved and the candidate has to first level line manage the people and their deliverables day to day. Responsibilities includes:Define technical specification in the area of ASIC IR/EM and PERC ESD domain for Intel advance technology features to enable Intel-specific and industry standard EDA design tools. Coordinate development of these technology features, develop QA plans and drive test-cases development working with relevant stakeholders.Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification. Joint effort with partners in DE organization to evaluate and isolate performance contributors for technology features as part of enablement. Build and qualify Process Pathfinding Kits and tools with quick turnaround time.Drive innovation and initiatives to enhance existing automation, tools and methodology. Identify and analyse problems, plans, tasks and solutions. Cultivate and reinforce appropriate group values, norms and behaviours. Perform in a dynamic, challenging and sometimes ambiguous environment with drive and creativity.The candidate should also exhibit the following behavioural traits and/or skillsCreative, independent, and out of the box thinker with strong problem-solving skills and analytical ability. Experience in driving cross-functional and industry wide initiatives and taskforces.Attention to details, strong organization skills. Depth and Breadth being able to connect the dots and identify cross-discipline optimal solutions. Self-motivated, strong leadership skills being able to influence across internal and external ecosystem\Written and verbal communication skills to present complex issues with clarity to drive decisions. Able to work with cross-functional and cross site teams and influence multiple internal and external stakeholders. Ability to work in a dynamic and team-oriented environment. Qualifications BS in EE/CS with minimum 10 relevant industry experience OR MS in EE/CS with minimum 8 years relevant industry experience OR Ph.D. in EE/CS with minimum 5-year relevant industry experience in the following areas: Minimum 5+ year of people management skill. Extensive experience in running all aspects of the IR and EM flows for ASIC designs, must be expert in Ansys RHSC and Cadence Voltus and other In design RV flows and solutions. In depth understanding of EM and IR flows methodologies using Ansys RHSC and Cadence Voltus. Deep expertise in PERC ESD rule deck development in either Siemens Calibre or Cadence Pegasus or Synopsys ICV rule decks, new process node PDK enablement in PERC ESD space. This includes both Schematic front end design and in back end layout design side of implementation. Device level knowledge in ESD operational physics, expertise in modelling lower nm technology ESD complications and new challenging implementation and advancements.-Expertise and multiple years of exposure in implementation or solving Schematic checks, LDL - p2p, CD checks in layout side. Planning, execution and validation of Strategic new initiatives in area of PERC ESD implementation, PDK rule decks and new EDA engagements. Parasitic Extraction, Device Modelling and Simulation tools/flows. Expertise in building testcases, automation to run these EDA tools and interpretation of the results. Familiar with Reliability verification in lower nm nodes, EM/IR and ESD concepts, IO cell design and ESD execution. Familiarity with TVF, TCL and python automation in deep expertise extent. ICV python rule deck implementation expertise is preferred domain area. Excellent communication skills, able to clearly articulate the requirements to EDA vendors. Project management skills, to effectively and independently own the ASIC RV(EM/IR) tools certification and ESD perc flow methodologies. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Mobile Repair Technician Mobile Phone repairs like replacements of Boards, Display panel, Battery & Camera components. Repair safety instructions. ESD & Repair Tools. Mobile software updates, and flashing OS. Jira tools.

Dear Applicant, Company ABAN Electronics (Advance tech Services Pvt ltd) Advance Tech was established in 1996 with a dream and determination to bring WorldClass Equipment, Tools & Consumables to India for Electrical, Electronics, Automobile, Pharma Industry and other commercial applications, including Electronic Maintenance. Profile – Sales Experience – 0-5yrs Location – PAN India Education – Graduate(minimum) or Diploma Responsibilities • Conduct market research to identify selling possibilities and evaluate customer needs • Actively seek out new sales opportunities through cold calling, networking and social media • Set up meetings with potential clients and listen to their wishes and concerns • Prepare and deliver appropriate presentations on products and services • Create frequent reviews and reports with sales and financial data • Ensure the availability of stock for sales and demonstrations • Participate on behalf of the company in exhibitions or conferences • Negotiate/close deals and handle complaints or objections • Collaborate with team members to achieve better results • Gather feedback from customers or prospects and share with internal teams Requirements and skills • Proven experience as a Sales Executive • Proficiency in English • Excellent knowledge of MS Office • Thorough understanding of marketing and negotiating techniques • Fast learner and passion for sales • Self-motivated with a results-driven approach • Aptitude in delivering attractive presentations NOTE – Candidates must have their own vehicle. Interested candidates can contact undersigned. Surbhi Negi 9711170281

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience :6+ years(A Must) Implementation with emphasis on Physical Verification & Hard macro/core finishing activities. Must have led and been primarily responsible for physical verification checks , fixing and sign-off. Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Deep understanding of ESD, latch-up etc. Own and execute PV activities at the Top/Block level. Work closely with PD team in addressing their PV issues and suggest solutions to them. Work with CAD team in refining the existing flows/methodologies and to resolve the issues. Experience in IO, Bump planning and RDL routing Strategy is a plus. Develop and implement timing and logic ECOs is a plus Innovus/FC level DRC fixing is a plus Python, PERL/TCL knowledge is a plus. Ability to plan and work independently and coordinate with cross-functional teams Has ability to close sign off DRC based on PNR markers is plus Skill Set: Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV. Good overall understanding of the Custom IC design flow. Good understanding of layouts and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. People management /Floorplanning/Power Planning/PDN experience is BIG Plus

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.