123 Esd Jobs

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node (180nm - 28nm) is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional

As an RFIC/MMIC Layout Engineer, you will be responsible for the design, planning, scheduling, and execution of Full Chip development involving analog and digital components. Your key responsibilities will include: - Performing Full chip feasibility and die size estimation for different bonding schemes - Demonstrating expertise in floorplan design, power schemes, signal planning, routing, physical verification, and quality check - Ensuring the delivery of quality full chip layout on-schedule while meeting design intent criteria such as Speed, Capacitance, Resistance, Power, Noise, and Area - Handling complex issues and using judgment to select appropriate methods for obtaining results - Establishing strong business relationships with cross-functional teams to facilitate project execution - Collaborating closely with Synaptic Global Analog and Digital Design and CAD engineering teams Your basic qualifications for this role include: - Bachelor's degree in electrical engineering, Electronics, Physics, or a related field - Experience in RF and MMIC design, with expertise in areas such as RF switches, power amplifiers, LNA, VCO, mixers, and couplers layout Preferred skills and experience that would be beneficial for this role: - Solid understanding of active and passive devices, circuits, and electrical fundamentals - Expertise in CMOS, FDSOI, and FinFET fabrication concepts, as well as Deep Nwell and triple well processes - Proficiency in analog layout techniques, electromigration, ESD, latch-up, crosstalk, shielding, and deep sub-micron challenges - Familiarity with SOC and ASIC design flows, procedures, and deliverables - Hands-on experience with tools such as Virtuoso L/XL/GXL, Calibre, PERC, STARRC, Totem, and ESRA - Strong analytical, debugging, and problem-solving skills to resolve layout design challenges and physical verification issues - Ability to work effectively in a cross-functional and multi-site team environment across different time zones - Excellent verbal and written communication skills This job description provides a comprehensive overview of the responsibilities and qualifications required for the RFIC/MMIC Layout Engineer role.,

Looking for Lab operation & Test lab management professional. Who can manage end-to-end test lab operations including RF & Telecom testing labs. Testing, repair & troubleshooting. lead lab planning budgeting & audits. apply now : npal@marquistech.com Required Candidate profile 6+ yrs exp in telecom/electronics must have hands-on lab setup, repair, calibration, ESD, audits & vendor mgt. IPC/ISO/NABL knowledge a must Location_ Noida Salary_ competitive hike on current package

Our vision is to transform how the world uses information to enrich life for . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Quality Program management Effective Work Environment controls(Clean room, ESD, etc) 12D Program management and Execution

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.

JD for Clean room Environment maintenance Technician Job Title: Clean room Environment monitoring Department: Cleanroom Operations / Quality Assurance / Facilities Location: Semiconductor Fabrication Facility (FAB) Reports To: Cleanroom Environmental Monitoring Engineer / Facilities Head Job Summary: The Cleanroom Particle Count Technician is responsible for performing daily Temperature, Rh, airborne particulate monitoring in classified cleanroom environments (ISO Class 5 to ISO Class 8) in a semiconductor manufacturing facility. The technician ensures strict compliance with ISO 14644 standards and internal protocols to protect wafer integrity and yield. Key Responsibilities: Conduct daily Temperature, Rh, airborne particle count measurements in cleanroom zones using calibrated laser particle counters . Ensure cleanroom conditions meet ISO Class 58 standards applicable to semiconductor manufacturing. Perform scheduled, unscheduled, and event-driven particle monitoring as per SOPs. Operate and maintain particle counters (e.g., TSI, Lighthouse, Met One), isokinetic probes, and supporting software. Accurately record, review, and trend data to detect deviations or contamination sources. Work with process engineers and facilities team to identify and resolve air quality issues . Report out-of-spec results immediately and support corrective action activities. Maintain logs and ensure all monitoring activities are properly documented and audit-ready. Participate in FAB requalification, tool hook-up validation , and HEPA filter testing support. Assist during internal audits and external inspections (ISO, ESD, EHS, customer audits). Ensure compliance with ESD protocols , cleanroom gowning , and movement procedures. Required Qualifications: Diploma / B.Sc / B.E / B.Tech in Electronics, Physics, Microbiology, Environmental Engineering, or related field Minimum 57 years of cleanroom monitoring experience in a Pharma/ semiconductor FAB or advanced electronics manufacturing Proficient in use and maintenance of laser particle counters and ISO 14644-1 requirements Familiar with semiconductor cleanroom protocols / GMP , tool qualification , and contamination control practices Ability to interpret trends and participate in root cause analysis (RCA) Skilled in using MS Excel, logbooks, and monitoring software Preferred Skills & Certifications: ISO 14644 awareness or training certificate Familiarity with SEMICON cleanroom standards , HVAC HEPA validation , or FAB protocols Knowledge of Statistical Process Control (SPC) for environmental data ESD awareness training Knowledge of FAB zoning & airflow control systems Work Environment: Requires working in Class 58 cleanroom environments in full gowning suit Shift work may be required (based on FAB schedule) Physical stamina to carry particle counters and remain in cleanroom zones for extended periods

We are looking for an IO Characterization Engineer with strong expertise in IO libraries and silicon validation. The candidate will work on advanced technology nodes, performing simulations, lab measurements, and delivering accurate characterization data for integration into sign-off tools. --- Responsibilities: Perform electrical characterization of IO circuits across process, voltage, and temperature (PVT) corners. Conduct silicon validation, ESD testing, signal integrity, and high-speed IO measurements. Develop automation scripts (Python/Perl/TCL) for data processing and analysis. Generate and validate timing, power, noise, and IBIS models for IO libraries. Debug and resolve silicon vs. simulation mismatches. Collaborate with design, CAD, and verification teams to improve IO quality and performance. --- Required Skills: 38 years of IO Characterization / IO Circuit Design experience. Proficiency in SPICE simulations and silicon measurement equipment (oscilloscopes, VNAs, BERT, etc.). Strong knowledge of CMOS IO design, ESD concepts, and signal/power integrity. Hands-on experience with IBIS, Liberty, HSPICE modeling flows. Expertise in Python, Perl, or TCL scripting for automation. --- Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, or VLSI.

Job Summary: We are seeking a detail-oriented Electronics Inspector with experience in inspecting cable harnesses, PCB assemblies, and electronic units. The role requires strong knowledge of IPC standards, harness assembly guidelines, ESD practices, and component-level inspection. The inspector will ensure electronic assemblies and subsystems conform to industry and customer specifications. Key Responsibilities: - Inspect cable harnesses for layout, crimp quality, conductor marking, continuity, and shielding integrity. - Perform visual inspection of PCBs and electronic units for soldering defects, component placement, polarity, and labeling. - Verify compliance to IPC-A-610, IPC/WHMA-A-620, and other applicable quality standards. - Conduct in-process and final inspections for wiring, termination, routing, bundling, and connector torque verification. - Use tools such as magnifiers, multimeters, continuity testers, and inspection checklists. - Ensure ESD-safe handling and inspection processes are followed. - Identify non-conformances and assist in root cause analysis and corrective action implementation. - Maintain inspection documentation, traceability logs, and defect tracking sheets. - Work with engineering and production to resolve quality issues and verify rework effectiveness. - Support internal audits and external quality compliance reviews.

Key Responsibilities: 1) 3+ years of experience in Production role with shopfloor experience. 2) Should have problem solving & good English communication skills. 3) Ability to handle manpower, Machine Production Planning, supervise the shop floor 35+ people. 4) Knowledge of ESD, 5S, KAIZEN, Continuous improvement & EHS. 5) Ability to communicate including verbal and written English. 6) Obtain required materials and tooling for assigned jobs 7) Prioritize and complete all tasks required to process product. 8) Manage time and efficiency to complete assigned job on time. 9) Identify, troubleshoot, and communicate any issues or problems encountered during setup or while processing product with respective concern teams. 10) Should be able to work in 12hr shifts.

As an Analog Circuit Design professional at Cadence, you will play a critical role in shaping the world of technology. With 2+ to 8 years of experience, your expertise will be utilized in our Hyderabad office. Your educational background should include a BE/B Tech/ME/M Tech/MS degree, and a deep understanding of high-speed Serdes/Memory interface circuits such as I/Os, PLLs, Clocking, and Datapaths is essential. Your hands-on experience with PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits will be highly valued. Proficiency in Analog Design, I/O Design fundamentals, and knowledge of ESD/Reliability/SI/PI is crucial. You will be expected to lead complex IPs, manage cross-functional dependencies, and mentor junior engineers. Moreover, prior exposure to advanced technology nodes like 16nm/10nm/12nm/7nm will be considered a significant advantage. Excellent written and verbal communication skills, along with strong problem-solving abilities, are essential for this role. At Cadence, we are committed to making a meaningful impact through our work. Join us in solving challenges that others cannot.,

Position : Assistant Manager Production Department : Production Department Organization Details : Greenfield Korean MNC Location : Pillaipakkam, Sriperumbudur Qualification : DME / BE Mech / EEE / CSE / Mechatronics Experience Details : 10 - 15 years preferably in Aerospace Industry Salary Details : 9 LPA 12 LPA Don't Call / WhatsApp Your Profiles : 6374071734 I 8825510083 / 8122463167 Job Description To control Manpower management and Ensure Effective Manpower Utilization in Shop Floor Managing and improving Production Capacity for customer demand to Achieve Plan vs Actual Ensure Operator safety and 55 in Shop Floor Inventory accuracy in Production store Manufacturing Rejection rate control Implement Lean, Six Sigma and Kaizen methodology to improve productivity Ensure Work Order closer in on time Experience in EMS Field and Known About ESD To improve OEE % & Knowledge about ERP and MES Tracking To Reduce TML and Scrap Rate Maintain Production Consumables stock SMT process knowledge and known about Rework process Good Knowledge in Report making Good communication skill -------------------------------------------------------------------------------------------------------------------------------- Position : Senior Engineer Production Department : Production Department Organization Details : Greenfield Korean MNC Location : Pillaipakkam, Sriperumbudur Qualification : DME / BE Mech / EEE / CSE / Mechatronics Experience Details : 6 - 10 years preferably in Aerospace Industry Salary Details : 6 LPA 9 LPA Don't Call / WhatsApp Your Profiles : 6374071734 I 8825510083 / 8122463167 Job Description To control Manpower management and Ensure Effective Manpower Utilization in Shop Floor Managing and improving Production Capacity for customer demand to Achieve Plan vs Actual Ensure Operator safety and 55 in Shop Floor Inventory accuracy in Production store Manufacturing Rejection rate control Implement Lean, Six Sigma and Kaizen methodology to improve productivity Ensure Work Order closer in on time Experience in EMS Field and Known About ESD To improve OEE % & Knowledge about ERP and MES Tracking To Reduce TML and Scrap Rate Maintain Production Consumables stock SMT process knowledge and known about Rework process ----------------------------------------------------------------------------------------------------------------------------- Position : Engineer Production Department : Production Department Organization Details : Greenfield Korean MNC Location : Pillaipakkam, Sriperumbudur Qualification : DME / BE Mech / EEE / CSE / Mechatronics Experience Details : 5 - 8 years preferably in Aerospace Industry Salary Details : 4 LPA 6 LPA Don't Call / WhatsApp Your Profiles : 6374071734 I 8825510083 / 8122463167 Job Description To Achieve Day/Month wise plan vs actual target Ensure good 55, operator safety and Discipline in Shopfloor Material management in Line To control Rejection rate in line Ensure ESD system in line Ontime Work order Closer To Reduce Downtime in shopfloor line Inventory accuracy In production Store SMT Process Knowledge --------------------------------------------------------------------------------------------------------------------------------- Position : Assistant Engineer Production Department : Production Department Organization Details : Greenfield Korean MNC Location : Pillaipakkam, Sriperumbudur Qualification : DME / BE Mech / EEE / CSE / Mechatronics Experience Details : 2 - 5 years preferably in Aerospace Industry Salary Details : 3.5 LPA 4.5 LPA Don't Call / WhatsApp Your Profiles : 6374071734 I 8825510083 / 8122463167 Job Description To Achieve Day/Month wise plan vs actual target Ensure good 55, operator safety and Discipline in Shopfloor Material management in Line To control Rejection rate in line Ontime Work order Closer To Reduce Downtime in shopfloor line ---------------------------------------------------------------------------------------------------------------------------------

Collaborate with crossfunctional teams on PCB layout&testing.Design embedded hardware using FPGAs,Cadence Allegro/Altium/Kicad/Autodesk Eagle.Responsibilities may evolve to meet the changing needs of the business.Mail CV's to: georgypthomas@gmail.com

You will be responsible for manual soldering of SMT & through hole components as well as cleaning. Additionally, wire harness preparation for internal, RF & Fiber optics cable will be a part of your job role. You should be familiar with handling chemicals like coating, potting & epoxy, and possess knowledge in similar areas of enhancements. Your tasks will also include ESD and online documentation, defect analysis and root cause implementation, self-inspection and rework, documentation reading and writing of observations to the Project team, and maintaining 5's standards. The ideal candidate should have a qualification of ITI - Electrician / Electronic Mechanic or Diploma - ECE / EEE with 2 to 3 years of experience in manual soldering. The position is located in Chennai and the company is Data Patterns (India) Limited. If you meet the qualifications and are interested in this Technician role, please send your resume to jobs@datapatterns.co.in.,

As a Physical Design Engineer based in Bangalore, India with over 3 years of experience, you will be responsible for various aspects of physical design for SoC using Innovus. Your key responsibilities will include floorplanning, IO ring creation, understanding ESD and latch-up requirements for foundry, and implementation strategies for placement. You will need to demonstrate expertise in hierarchical design implementation, including partitioning, push down methodologies, core/tile PG creation, and knowledge of analog components placement based on design specifications. Additionally, RDL knowledge and experience working with packaging are essential for SoC floorplan design. A critical aspect of your role will involve PV clean-up on the floorplan and ensuring compliance with Physical Verification, ESD, foundry, and analog requirements. Deep scripting knowledge is a prerequisite for this position, along with strong problem-solving capabilities, proactive attitude, hardworking nature, and excellent interpersonal skills. To qualify for this role, you must hold a Bachelor's Degree in Electrical, Electronics, or Computer Engineering. If you are looking to leverage your experience and skills in physical design within a dynamic and innovative environment, this opportunity is tailored for you.,

The ideal candidate for this position should possess the following experience and skills: - Strong problem-solving abilities. - Excellent communication skills. - Proficiency in Electronic Circuit Design. - Familiarity with hardware design tools such as Kicad or similar software. - Experience in Multilayer PCB design would be a plus. - Good understanding of design considerations for EMI / ESD. If you believe that your profile aligns with the requirements mentioned above, please feel free to submit your resume via email to careers@emprotek.com.,

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

As a Safety System Engineer specializing in ABB Safety HI system, your primary responsibility will be to design, develop, and deploy high-integrity safety systems for industrial applications. Your focus will be on ensuring and maintaining high levels of operational safety and integrity within the systems. You will be required to set up, configure, and commission ABB high-integrity safety solutions based on project requirements and industry standards. Your role will involve providing technical expertise in ESD, PSD, F&G, and C&E, including programming safety logics, HMI interface, testing, and functional verifications. In this position, you will need to interpret P&IDs and control narratives, and prepare technical documentation such as FDS, IO lists, operation manuals, and test procedures. Additionally, you will execute ethernet network configurations and communication protocols essential for safety networks. Your responsibilities will also include conducting risk assessments and hazard analyses to identify and mitigate risks associated with safety systems. You will be expected to identify opportunities for optimizing system performance and reliability, and collaborate with the engineering team to implement necessary improvements. To be successful in this role, you should hold a graduate degree in engineering with over 10 years of experience in safety system engineering with a specialization in ABB Safety HI system. It is essential to have expertise in Pre-FAT, FAT, installation, and commissioning of safety systems. Being TUV and FSM certified is a requirement for this position. A solid understanding of plant safety concepts such as ESD, PSD, F&G, C&E, and Pressure protecting systems is necessary. You should have a proven track record in leading large-scale safety projects, preferably within industries like Oil & Gas, Petrochemical, or manufacturing sectors. Moreover, excellent written and verbal communication skills are crucial for effectively conveying complex technical information in this role.,

Manage Following, Lead Instrumentations, Diagrams, Control systems (DCS, PLC, SCADA, ESD) Compliances, Technical Evoultion, SPI, AutoCAD/EPLAN, and other relevant software, Functional Safety Standards, Loop checking, pre-commissioning. Required Candidate profile Apply functional safety standards (e.g., SIL, HAZOP); knowledge of TV or equivalent certification is a plus.

Hi, We are hiring for EMI/EMC Test Engineer for Mysore/Mysuru location. Job title: EMC Testing Engineer Openings: 2-3 Work Location: Mysore/Mysuru and Chennai Division/Department: EMC lab Profile: The EMC Test Engineer is responsible for evaluating, explaining, and completing the test report for intricate customer samples. Follows defined test plans, testing procedures and data sheets for the product under test. Operates and maintains complex test equipment and customer samples. Communicates with customers during setup and operation to ensure proper evaluation. Skills required: strong background in EMC/EMI testing. Knowledge of basic EMC standard like Knowledge of EMC standard like IEC 61000-4 series, IEC 61326, MIL standard, IEC62052-11 series and CISPR series. Knowledge of Emission and Immunity test like Radiated and Conducted emission, ESD, EFT, Surge, Conducted and Radiated Susceptibility test. Exposer of testing in 3M Anechoic chamber. Experience: Minimum 4 years Educational Qualification Required: B.tech/Diploma (E&C/E&E) or M.tech (E&C/E&E). Interested candidates please share your updated resume to nikita.singh@nemko.com or apply here on naukri.com

As an Analog Layout Design Engineer at Synopsys, you will play a pivotal role in developing cutting-edge layouts for next-generation DDR/HBM/UCIe IPs. Your primary responsibilities will include creating floorplans, routing, and conducting physical verifications to ensure high-quality deliverables that meet stringent quality standards within specified timelines. You will collaborate closely with design engineers to optimize layouts for performance, power efficiency, and area utilization. By implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, you will contribute to the enhancement of the performance and reliability of semiconductor IPs. Ensuring compliance with DRC, LVS, ERC, and antenna rules will be a key part of your role to mitigate risks associated with layout design. Your expertise in deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies at 7nm and below will be crucial in driving the development of high-performance silicon chips. Your problem-solving skills, along with effective communication abilities, will enable you to work efficiently with cross-functional teams and convey complex technical concepts concisely. As a valuable member of the team at Synopsys, you will contribute to the mission of leading in chip design and software security by accelerating time-to-market for innovative technologies while fostering a collaborative and inclusive work environment. Your commitment to continuous learning and professional development will be instrumental in your success within our dynamic and innovative team. Join us at Synopsys to be a part of a forward-thinking organization that values collaboration, inclusivity, and continuous improvement. We offer a comprehensive range of rewards and benefits to cater to your needs, including health, wellness, and financial benefits. Your recruiter will provide you with more details about the salary range and benefits during the hiring process.,

Job Description: As an Analog Layout Engineer at SILCOSYS Solutions Pvt. Ltd., you will be responsible for custom circuit layout, physical verification, and RC extraction. We are looking for a talented individual with 3 to 7 years of experience in the field. Proficiency in Cadence Virtuoso and a solid understanding of DRC, LVS, and DFM methodologies are essential for this role. Key Requirements: - Demonstrated expertise in AMS and high-speed layout design - Exposure to components such as Temperature Sensors, SRAM, TCAM, ROM, MRAM, ESD - Track record in advanced technology nodes, with experience in 5nm/3nm considered a plus - Familiarity with Totem EMIR tools and methodologies This position offers a unique opportunity to contribute to cutting-edge semiconductor technologies within a dynamic and innovative work environment. If you meet these qualifications and are ready to take on this exciting challenge, please share your resume with us at info@silcosys.com. We are looking forward to hearing from you!,

At Capgemini Engineering, the world leader in engineering services, you will be a part of a global team of engineers, scientists, and architects dedicated to helping the world's most innovative companies reach their full potential. From cutting-edge technologies like autonomous cars to life-saving robots, our digital and software technology experts are always thinking outside the box to provide unique R&D and engineering services across all industries. Join us for a rewarding career filled with endless opportunities where you can truly make a difference, and where no two days are ever the same. As an Analog Layout Designer, you will work independently on block-level analog layout design tasks, encompassing everything from Floorplan to Routing and Verifications. Your role will involve hands-on experience in the critical analog layout design of various blocks such as Temperature sensors, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, and Differential Amplifiers, among others. You should possess a strong proficiency in LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. A solid understanding of concepts such as Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel effects is essential for this role. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is a must. You should also be able to comprehend how layout decisions impact circuit performance metrics like speed, capacitance, power, and area, and effectively implement design constraints to produce high-quality layouts. Experience with multiple tape outs will be advantageous, along with possessing good interpersonal skills and critical thinking abilities to address technical issues professionally. Excellent communication skills are vital for this role, as you will be responsible for executing layout designs in a timely manner while maintaining high quality standards. Key Skills: - Analog Layout Design - Process or technology experience: TSMC 7nm, 5nm, 10nm, 28nm, 45nm, 40nm - EDA Tools: Cadence Virtuoso Layout Editor (L, XL), Physical verification tools (DRC, LVS, Calibre) In summary, this role at Capgemini Engineering offers a dynamic opportunity to work on challenging projects, collaborate with a diverse team of professionals, and contribute to the advancement of innovative technologies across various industries. If you are someone who thrives in a fast-paced and cutting-edge environment, we welcome you to join us on this exciting journey towards engineering excellence and innovation.,

Position Name : SMT AOI Engineer (JET Model) Location : Hyderabad Experience : Minimum 8 Years CTC : Up to 12 LPA Job Description / Responsibilities Operate, program, and maintain SMT AOI (Automated Optical Inspection) JET Model equipment. Perform inspection of PCB assemblies to identify defects and ensure compliance with quality standards. Analyze AOI results, verify defects, and coordinate with production/quality teams for corrective actions. Conduct regular preventive maintenance and calibration of AOI equipment to ensure maximum uptime. Collaborate with cross-functional teams (SMT process, quality, production) to enhance yield and reduce defects. Prepare inspection reports, maintain process documentation, and ensure adherence to industry standards. Candidate Profile Minimum 8 years of experience in SMT AOI (JET Model) operations and maintenance. Strong knowledge of PCB assembly processes and SMT equipment. Ability to troubleshoot AOI-related issues and optimize inspection programs. Good understanding of IPC standards and electronics manufacturing processes. Excellent analytical and problem-solving skills. Education Diploma / BE / B.Tech in Electronics / Electrical / related discipline. Role SMT AOI Engineer / Specialist Industry Type Electronics Manufacturing / EMS Department Production, Manufacturing & Engineering Employment Type Full Time, Permanent Role Category Operations, Maintenance & Support Key Skills SMT AOI, JET Model, PCB Assembly, Automated Optical Inspection, SMT Process, Electronics Manufacturing, Troubleshooting, Preventive Maintenance, IPC Standards

Should have experience in SIS ( Safety instrumented system), Safety Documentation, ESD, FSG, IEC, PLC, Safety software, Safety Instrumentation, Gas Detectors.

Role & responsibilities 1 Job description Perform routine maintenance and troubleshooting test jigs and related equipment. Inspect and calibrate test jigs to ensure accurate and consistent testing results. Coordinate with Test Infrastructure team” to identify and resolve any issues with test equipment. Document all maintenance, repairs, and modifications performed on test jigs. Maintain an inventory of spare parts and tools necessary for test jig maintenance. Perform regular quality inspection activities for mechanical and electronic items as per Quality Plan. Carry out calibration activity for in-house equipment as per plan. Co-ordinate with external calibration agencies to complete calibration as per plan. Maintain master list of calibration and reports. Co-ordinate with production for in-process failures Support in ESD Compliance Verification 2 Key roles & responsibilities Carry out jig maintenance as per TPM plan and keep record. Calibrate the in-house tools and equipment as per instruction and keep record. Attend sudden issues in test jig and co-ordinate with TI to solve the issue. Ensure that test jigs comply with relevant safety standards and protocols. Procure the spares and maintain stocks for jig maintenance. Conduct regular process audits to ensure compliance with internal and external quality standards, such as ISO or IPC standards. Send instrument to calibration agencies, obtain, verify, and maintain calibration reports. Prepare and maintain all maintenance report, history cards. Carry out regular inspection and prepare inspection reports. Carry out monthly ESD Compliance verification as per check list. Follow up with all locations to complete the site related tools and equipment calibration. Review test data and prepare reports on quality metrics, including yield rates, failure rates, and root cause analysis. Implement process improvements to enhance the overall efficiency and accuracy of PCB testing. 3 Authorities Authorized for product acceptance or rejection during incoming inspection. The engineer has the authority to assess the condition of jigs, tools, and fixtures used in production anytime. Authorized to carry out or recommend maintenance to malfunctioning or worn-out jigs. The engineer can propose modifications or improvements to enhance the performance, efficiency, or lifespan of jigs based upon observations during maintenance. The engineer has the authority to calibrate jigs to ensure they meet the precise tolerances and specifications required for production. 4 Qualification & required technical skill sets Diploma of engineering graduate in Electronics Engg. with 1-2 years of experience. Familiar with test jigs, instrument calibration, part inspection. Familiar with electronics components, PCBA 5 Personal attributes Proactive Problem solving Attention to detail. Adaptability Team collaboration 6 Technical attributes Troubleshooting and Maintenance Knowledge of Testing Equipment Understanding of Electrical Standards Understanding of Calibration 7 Work location FR IN, Mysore office Preferred candidate profile