26 Pll Jobs

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor's, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers' and clients' business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Job Area: Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Lead design of analog/mixed-signal ICs (ADC/DAC, PLL, LDO/DCDC, IO Drivers). Oversee verification, layout compliance, cross-functional collaboration, and product support. Utilize EDA tools for design, simulation, and debugging. Required Candidate profile Experienced analog/mixed-signal IC designer (8+ yrs), adept in variation-aware design, verification, debugging, and product support. Strong in cross-functional collaboration. Masters in VLSI or ECE

Were looking for a skilled Analog/RF ASIC Design Engineer to join our team. This role is ideal for someone with a strong background in RFIC or analog IC design , and hands-on experience with Cadence Virtuoso . Preferred candidate profile 8+ years of experience in Analog or RF IC design . Strong hands-on skills with Cadence Virtuoso and analog simulation tools. Experience with PLL or other high-frequency analog circuits. Solid understanding of analog design fundamentals (noise, matching, stability, etc.). Bachelors or Master’s degree in Electrical or Electronics Engineering.

General Summary: Qualcomm is seeking an experienced and driven Silicon Characterization Engineer to join its hardware engineering group, contributing to the development and validation of industry-leading SoCs. This role focuses on post-silicon validation and characterization of high-performance silicon components such as PLLs , oscillators , and SoC subsystems , ensuring product reliability, performance, and quality. You will work in close collaboration with cross-functional teams, leveraging strong expertise in firmware development , semiconductor fundamentals , and lab instrumentation to execute detailed electrical characterization, develop automation flows, and perform root-cause analysis on silicon behavior. Key Responsibilities: Lead and execute PnP (Performance and Power) characterization of SoCs, including modules like PLLs and oscillators. Develop and validate firmware for multi-core microcontrollers or processors (ARM, RISC-V). Use lab tools (oscilloscopes, logic analyzers, spectrum analyzers, power meters, etc.) for detailed measurements and silicon debug. Automate test and measurement processes using Python scripting to streamline workflows and improve coverage. Analyze silicon performance and compare it against design specs to identify and investigate anomalies. Collaborate with silicon design, DFT, validation, and test teams to optimize test coverage and debug support. Contribute to characterization reports , silicon bring-up plans, and release documentation. Minimum Qualifications: Bachelor's degree in Electrical Engineering , Computer Engineering , or related field and 2+ years of experience in hardware engineering or silicon validation. OR Master's degree with 1+ year of relevant experience. OR PhD in a relevant field. Required Skills: 515 years of hands-on experience in silicon characterization or validation . Deep knowledge of CMOS device operation, solid-state physics , and submicron FET architectures . Strong background in firmware development for embedded platforms (C/C++ for ARM/RISC-V cores). Proficient in Python scripting and automation of lab equipment. Proven experience with automated characterization flows to maximize lab efficiency. Familiarity with semiconductor test and measurement equipment and methodologies. Strong problem-solving skills, attention to detail, and ability to drive root-cause investigations. Self-motivated with excellent initiative and organizational discipline. Preferred Qualifications: Experience in high-volume silicon validation environments . Knowledge of semiconductor manufacturing , test methodologies, and yield optimization. Understanding of thermal and power analysis in SoC systems. Exposure to lab automation frameworks and test data analytics. Key Traits: Strong analytical thinker with a proactive and hands-on approach to problem-solving. Highly collaborative and communicative, capable of working across interdisciplinary teams. Committed to continuous learning and staying updated with semiconductor trends.

Job Requirement: We are looking to hire engineers with 5 to 10 years of experience in Analog circuit design. Candidate needs to have comprehensive knowledge of Analog design with experience in some blocks like OpAmps, Comparators, Bandgap References, LC and ring oscillator, PLLs, CDR, LDO, Tx/Rx etc Should have understanding of process technologies and device behaviour and reliability issues, ESD and latchup Should have understanding of various aspects of signal integrity. Experience in Rx, Tx, T-coil ESD, CDR, equalization techniques like CTLE/DFE in PCIE or Ethernet is preferred. Strong documentation skills and collaborative attitude are must haves

About The Role Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsB.E/ B.Tech Electronics/Electrical/VLSI Design Engineering with 3+ years of relevant experience in Analog and IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, LVDS etc.Preferred Qualifications:Analog Device and Metal Layout FundamentalsAnalog/Mixed Signal FundamentalsReliability Verification.Cadence Virtuoso Layout Suite Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Analog Mixed Signal Layout Location: Bangalore, Hyderabad, Noida Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Experience (years) : 3 - 7 Years Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

• EXP. of Analog blocks like Op-amps, BGR’s, LDO’s, PLL’s , Clocking circuits, TX / RX. • Analog circuit in PMIC domain: Design of Voltage/Current references, Amplifiers, Comparators, Filters & Voltage sensors, Oscillators, Voltage clamps. Required Candidate profile • EXP on High Speed SERDES/ Memory Circuits is PLUS • Exposure to cutting edge technology nodes like FinFets is PLUS • Hands-On atleast 2/ 3 of Blocks • Strong Analog Design Fundamentals

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We are hiring for multiple positions in this team, you can refer the JD below for more information on each of the roles open. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. CPU Silicon Bring up and Validation Engineer The charter for CPU Silicon Bringup team would be to prepare for and support bring up of every SoC using the Custom CPUs - from first Silicon through to productization. Roles and Responsibilities: Work with CPU design and verification teams to develop CPU bring up and validation test plans. Prepare for CPU bring up through pre-work on emulation and FPGA platforms. Work with SOC bring up teams, software teams to plan CPU bring up. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringups. Minimum Requirements: BA/BS degree in CS/EE with 5+ years experience. 3+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Preferred Requirements: Strong understanding of micro-processor architecture. Strong understanding of power management, physical design concepts. Experience in Silicon bring up and validation of CPU features. Experience in debug of functional, power, performance and/or physical design issues in silicon. Experience in CPU design and verification. Experience in Test development for validation of CPU features on Silicon. Experience in development of test vectors for tester bring up. Post-Sil Power & VMin characterization Engineer 5 to 15 years of experience in Silicon characterization or silicon validation Expertise in the characterization of SoC, PLL, Oscillators, etc. Firmware Development on multi-core microcontrollers or processors (ARM/RISC-V or similar) Experience working in a laboratory environment, familiarity with using lab equipment such as logic analyzers, spectrum analyzers, oscilloscopes, function generators, etc. Knowledge of electrical engineering fundamentals including CMOS device operation and characteristics Good understanding of semiconductor technology, solid state device physics and submicron FET architectures Good Experience in Python scripting Exposure to automated characterization flows to maximize use of equipment Initiative (self-motivated, self-confident, self-driven, self-learning, always striving for excellence) Good analytical skills and problem solver. Post-Silicon CPU Debug Engineer Defining Debug Enabling Tools Strategy for next gen CPU product line before designexecution Defined DFD Hardware Validation Strategy defining the overall scope of validation,aligning with customers and architecture/micro-architecture teams, effort estimations, equipment, platform, and other logistics required for the validation, etc. Driving DFD Domain defining the validation coverage metrics across all the validation teams engaged right from HW design through post-silicon and beyond. Identifying the coverage gaps between the teams and driving it with additional test case additions in their respective plan. Be the customer voice for DFD Architecture/micro-Architecture owners and provide detailed feedback on DFD feature definition/implementation in terms of meeting customer requirements. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 5 to 15 years of experience in Silicon characterization or silicon validation Expertise in the PnP characterization of SoC, PLL, Oscillators, etc. Firmware Development on multi-core microcontrollers or processors (ARM/RISC-V or similar) Experience working in a laboratory environment, familiarity with using lab equipment such as logic analyzers, spectrum analyzers, oscilloscopes, function generators, etc. Knowledge of electrical engineering fundamentals including CMOS device operation and characteristics Good understanding of semiconductor technology, solid state device physics and submicron FET architectures Good Experience in Python scripting Exposure to automated characterization flows to maximize use of equipment Initiative (self-motivated, self-confident, self-driven, self-learning, always striving for excellence) Good analytical skills and problem solver. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Analog Validation/Characterization Engineer/Lead

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

Job Area: Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries " from automotive to health care, from smart cities to robotics" we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU DesignMust have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skillEducational Background:Masters, Bachelors:Electrical Engineering , VLSI , Embedded and VLSI , ECE

About The Role : Lead low power validation strategy and drive validation roadmap across multiple projects Lead a very high performing team of talented engineers working on GPU IP post-Si low power validation Excellent understanding latest GPU architecture/micro-architecture low power features, design changes and develop Post-Si Low Power validation test plan for 3D/Compute pipeline Very good understanding of low power concepts and flows (dynamic, leakage power, clock gating, power gating, Resets, stand-by entry/exit flow, DVFS, clock squashing, TDP, PM flexing) Good understanding of power switching, isolation, level shifter, clock domain crossing, PLL, power delivery logic Understanding of low power FSM blocks, states and interfaces with microcontrollers, SW Driver, FW, SoC and platform Define low power validation scenarios and implement basic/stress/concurrency/cross-feature/PM cycling/random test cases Work closely with pre-Si architect/design/verification and SW/FW teams to review test plans and scenarios and finalise synthetic/BareMetal/driver/real use cases to validate on simulation/emulation to sanitize tests before Si arrival Analyse feature coverage gaps and enhance test plans Define power-on bring up and volume validation regression plan to enable PRQ. Come up with receivables/dependencies, Risks/mitigation and follow-up closely with relevant stakeholders for closure Debug:Understand Si failure signatures in-depth, work closely with design and architecture, SW/FW teams to root cause issues. Guide juniors on debug Tools : Advance usage of Si debug tools. Work with tool development teams to Develop tools/scripts. Effective reproduction of issue on Emulation/simulation to decrease debug TAT Innovation - Drive development of new low power validation methodologies, shift-left validation, PM test framework, automation tools (test content generation, debug, feature coverage) and adoption of AI/ML methods to improve efficiency Regular Rolling up of the Post Si low power validation status to the upper management for decisions at various product cycle milestones Qualifications Master of Engineering degree in Computer or Electronics or Embedded Systems Engineering with 7+ years' experience in graphics post silicon power management PhD degree in Computer or Electronics or Embedded Systems Engineering with 5+ years' experience in graphics post silicon power management Should have good understanding of Computer architecture, Graphics architecture/design, low power Validation and Si Debug Flow Hands-on experience in C/ C++, and Perl/Python, Linux Shell Scripting Familiarity with Verilog/System Verilog/VHDL Familiarity with Windows, Linux OS, commands and environment Familiarity with OpenCL, OpenGL, Vulkan and DirectX API programming is desirable. Good analytical ability, problem solving, and written and verbal communication skills Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

• Hands –On EXP. on atleast 2/ 3 of Analog Blocks • Good Understanding of Analog blocks like Op-amps, BGR’s, LDO’s, PLL’s , Clocking circuits, TX / RX. • EXP. on High Speed SERDES/ Memory Circuits is a Plus Required Candidate profile • Exposure to cutting edge technology nodes like FinFets is a Plus • Strong Analog Design Fundamentals

Job Title: Analog Circuit Design Engineers Design of LDOs, Bandgaps, Temp Sensors, PLLs, GPIOs and other analog blocks Design of SERDES blocks like Transmitters, Receivers, Equalizers, Calibration and compensation blocks.

Senior Analog Manager /Manager /Lead ( HBM / IO ) www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. Job Description: Sevya is architecting and designing a HBM transceiver in advanced FinFET node. Sevya needs analog designers at all levels with skills in the areas of analog circuit design, custom digital design for SerDes and other high speed IP applications, signal and power integrity modeling, pre and post silicon debug. Familiarity with HBM, DDR and other memory standards in highly desirable but not necessary if the candidate has good knowledge of high speed design. Candidates with experience of linear circuits such as high bandwidth LDOs, amplifiers, charge pumps etc. who want to explore high speed design are also welcome, we have appropriate work and there will be opportunities to learn more. Specifically we are looking for people with approximately 10-15 yrs of experience for Senior mnager positions and 7-10 yrs for lead positions. Candidates with higher experience also welcome for appropriate role. Responsibilities: I/O Architecture Design: Develop and design the input/output architecture for integrated circuits using HBM technology. Signal Integrity Analysis: Perform signal integrity analysis to ensure reliable and high-speed data transfer between the HBM memory and the rest of the system. Circuit Design: Design and optimize circuits for HBM I/O interfaces, considering factors such as power consumption, area, and performance. Collaboration: Work closely with cross-functional teams, including system architects, memory designers, and layout engineers, to ensure seamless integration of HBM I/O interfaces into the overall system. Standards Compliance: Ensure that HBM I/O designs comply with industry standards and specifications, such as JEDEC standards for high-bandwidth memory. Simulation and Modeling: Utilize simulation tools and models to validate the design's performance and address any potential issues related to signal integrity, power delivery, and thermal considerations. Debugging and Troubleshooting: Identify and resolve issues during the testing and debugging phases of the design process. Documentation: Prepare detailed documentation of the HBM I/O design, including specifications, test plans, and design guidelines. Requirements: Bachelor's degree or higher in Electrical Engineering or a related field. A minimum of 7-15 years of experience in analog circuit design within the semiconductor industry. Proven expertise in designing analog blocks, including Bandgap references, PLLs, LDOs, and High-Speed I/O circuits. Proficiency in industry-standard Electronic Design Automation (EDA) tools for analog design and simulation. Strong knowledge of semiconductor fabrication processes and technologies. Exceptional problem-solving and analytical skills. Effective communication and teamwork abilities. Preferred Qualifications: - Experience in mixed-signal circuit design. - Familiarity with high-speed data communication interfaces. - Knowledge of low-power design techniques. - Published research or patents related to analog design. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Analog Manager /Manager /Lead ( HBM / IO ) www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. Job Description: Sevya is architecting and designing a HBM transceiver in advanced FinFET node. Sevya needs analog designers at all levels with skills in the areas of analog circuit design, custom digital design for SerDes and other high speed IP applications, signal and power integrity modeling, pre and post silicon debug. Familiarity with HBM, DDR and other memory standards in highly desirable but not necessary if the candidate has good knowledge of high speed design. Candidates with experience of linear circuits such as high bandwidth LDOs, amplifiers, charge pumps etc. who want to explore high speed design are also welcome, we have appropriate work and there will be opportunities to learn more. Specifically we are looking for people with approximately 10-15 yrs of experience for Senior mnager positions and 7-10 yrs for lead positions. Candidates with higher experience also welcome for appropriate role. Responsibilities: I/O Architecture Design: Develop and design the input/output architecture for integrated circuits using HBM technology. Signal Integrity Analysis: Perform signal integrity analysis to ensure reliable and high-speed data transfer between the HBM memory and the rest of the system. Circuit Design: Design and optimize circuits for HBM I/O interfaces, considering factors such as power consumption, area, and performance. Collaboration: Work closely with cross-functional teams, including system architects, memory designers, and layout engineers, to ensure seamless integration of HBM I/O interfaces into the overall system. Standards Compliance: Ensure that HBM I/O designs comply with industry standards and specifications, such as JEDEC standards for high-bandwidth memory. Simulation and Modeling: Utilize simulation tools and models to validate the design's performance and address any potential issues related to signal integrity, power delivery, and thermal considerations. Debugging and Troubleshooting: Identify and resolve issues during the testing and debugging phases of the design process. Documentation: Prepare detailed documentation of the HBM I/O design, including specifications, test plans, and design guidelines. Requirements: Bachelor's degree or higher in Electrical Engineering or a related field. A minimum of 7-15 years of experience in analog circuit design within the semiconductor industry. Proven expertise in designing analog blocks, including Bandgap references, PLLs, LDOs, and High-Speed I/O circuits. Proficiency in industry-standard Electronic Design Automation (EDA) tools for analog design and simulation. Strong knowledge of semiconductor fabrication processes and technologies. Exceptional problem-solving and analytical skills. Effective communication and teamwork abilities. Preferred Qualifications: - Experience in mixed-signal circuit design. - Familiarity with high-speed data communication interfaces. - Knowledge of low-power design techniques. - Published research or patents related to analog design. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Design and development of analog and mixed-signal IC blocks such as amplifiers, ADCs/DACs, voltage regulators, PLLs, bandgap references, and filters. Perform transistor-level circuit design, simulations (pre- and post-layout), using cadence Virtuoso.