Job
Description
Bachelor or master Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high speed layout, e. g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus. Good communication skills and willingness to work with global team. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment Work Experience Must have expertise on Totem EMIR Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus.
