Std. Cell Layout Design Engineer

2 - 7 years

1 - 5 Lacs

Posted:1 day ago| Platform: Naukri logo

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Work Mode

Work from Office

Job Type

Full Time

Job Description

Location:

Bangalore, India

Experience:

2+ Years

Notice Period:

Immediate to 1 Month Preferred

About Genisup India Private Limited

Genisup India Private Limited is a leading semiconductor and system design company headquartered in Bangalore. We specialize in Foundational IP Fabless Design, Semiconductor & Product Engineering, and IoT solutions. Our client portfolio includes top-tier companies such as NXP, Qualcomm, and Analog Devices. We are committed to delivering innovative solutions and technical excellence in the semiconductor industry.

Role Overview

We are looking for an experienced Senior Analog Layout Design Engineer with strong expertise in standard cell layout design to join our team. In this role, you will be responsible for designing, developing, and modifying full custom layouts for standard cells across advanced process nodes. Youll contribute to floorplanning from sub-block to chip top level while ensuring design rule compliance and optimal performance. Immediate joiners or candidates with up to a 1-month notice period are preferred.

Key Responsibilities

  1. Design, develop, and modify full custom layout designs for Standard Cells
  2. Execute floorplanning from sub-block to chip top level
  3. Implement hierarchical layout assembly and standard cell planning
  4. Improve and determine methods and procedures for layout development flow to ensure efficiency and accuracy
  5. Collaborate with design engineers to optimize layout designs for performance and manufacturability
  6. Conduct layout verification and ensure compliance with design rules and specifications
  7. Interpret CALIBRE DRC, LVS, ANT, EM/IR results and address issues effectively
  8. Implement solutions for reliability concerns including ESD, Electro migration & IR, and Latch-up
  9. Provide technical guidance and mentorship to junior layout engineers

Required Qualifications

  1. BTech in Electronics or related field
  2. 2+ years of hands-on experience in standard cell layout design
  3. Experience working with FDSO 22nm, CMOS 28nm, 40nm, 16nm ffc and beyond process nodes
  4. Proficiency with Cadence Virtuoso Design suite
  5. High-level expertise in layout floorplanning and hierarchical layout assembly
  6. Strong understanding of DRC, LVS, ANT, and EM/IR verification techniques
  7. Demonstrated knowledge of reliability issues (ESD, Electro migration, Latch-up)
  8. Excellent analytical and problem-solving abilities
  9. Strong communication skills and ability to mentor junior team members

Preferred Skills

  1. Scripting experience in CSH, PERL or SKILL
  2. Experience with advanced FinFET technology nodes
  3. Knowledge of parasitic extraction and back-annotation
  4. Familiarity with design for manufacturing (DFM) techniques
  5. Experience with custom analog circuit layout optimization

Why Join Genisup

  1. Work with industry-leading semiconductor technologies
  2. Collaborate with a team of technical experts on cutting-edge projects
  3. Clear path for professional growth and advancement
  4. Competitive compensation package
  5. Dynamic and innovation-focused work environment

Join Genisup and be a part of a team that is pushing the boundaries of chip design! We offer a competitive compensation package and a stimulating work environment.

Genisup India is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, gender, national origin, age, or any other protected characteristics.

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