Sta Engineer

Mirafra

4 - 9 years

20 - 35 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

primetime sta synthesis timing closure static timing analysis

Work Mode

Work from Office

Job Type

Full Time

Job Description

Mirafra Technologies Hiring STA Engineers:

STA/Synthesis :

Experience in handling complex data path oriented Multi-million gate synthesis.
Working Knowledge on Physical synthesis using tools like Genus, Fusion Compile.
Experience in debugging for multi-clock domains hierarchical/flat timing analysis
Good working knowledge in multi-power domain synthesis and structural power checks using CLP.
Hands-on experience in Formal verification along with strong debugging skills for resolving issues/aborts.
Good Experience in synthesis timing closure and interactions with DFT and PD.
Good knowledge on analyzing trade-offs and recipes for timing/area/power/congestion.
Exposure in TCL scripting for usage in Synthesis/STAGood team player. Need to interact with the stakeholders proactively
Good verbal and written communication skills
Ability to debug and solve issues independently

Job Description

Static Timing Analysis and Closure.
Main responsibility of the candidate will be around timing closure domain with below key items: Timing closure for Arm CPU implementation
Should have completed multiple tape-outs with timing closure role in the past.
Strong understanding of STA and timing concepts.
Need to run STA across multiple modes and corners.
Needs to work on setup, hold, DRV and other types of timing fixes across tools like Synopsys PrimeTime, Cadence Tempus, Synopsys Tweaker, and others.
Needs to be well versed with timing constraints handling.
Need to undergo some ECO cycles to meet performance targets.
Need to be conversant of power optimization techniques!

Interested candidates share resume at sayantikamajumdar@mirafra.com

Thanks

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