238 Cadence Virtuoso Jobs - Page 10

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineer...

About The Role Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Analog Layout Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will be responsible for developing and configuring software systems, either end-to-end or for specific stages of the product lifecycle. Your typical day will involve collaborating with vari...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Analog Layout Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to perform maintenance and enhanc...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, your typical day involves analyzing, designing, coding, and testing various components of application code across multiple clients. You will engage in maintenance and enhancement tasks, ensuring that the software remains efficient and effective. Coll...

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr/ Staff Analog Layout Engineers: 7nm/ Lesser with DDR Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 5-8 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking a highly skilled Analog Mixed-Signal (AMS) Layout Engineer with proven expertise in 7nm or smaller technology nodes , FinFET architecture , and DDR interface layouts . The ideal candidate will work closely with design teams to deliver high-performance, low-power, and area-efficient layouts for cutting-edge semiconductor produc...

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr Analog Layout Engineers: High Speed: 7nm/ Lesser Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 3-5 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking an Analog Mixed-Signal (AMS) Layout Engineer with deep expertise in 7nm or smaller process nodes , FinFET technologies , and high-speed layout design . The ideal candidate will have hands-on experience in complex analog, digital, and mixed-signal layouts, ensuring optimal performance, power, and area for cutting-edge semiconductor...

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology no...

Job Title: Senior EDA Engineer - Cadence Virtuoso, SKILL/CDF, Tool Integration Role Overview: We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform. Key Responsibilities: Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Create, modify, and optimize SKILL scripts for automation of layout, schematic...

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualificatio...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...

Job Title: Senior EDA Engineer Cadence Virtuoso, SKILL/CDF, Tool Integration Role Overview: We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform. Key Responsibilities: Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Create, modify, and optimize SKILL scripts for automation of layout, schematic, ...

Physical Verification Engineer As a Physical Verification Engineer, you will play a leading role in the physical design domain for developing Onsemi s cutting edge image sensor products You will work on the physical verification (PV) flow and chip closure activities You need to work closely with the cross-functional teams like physical/Analog design, PDK, IP, ESD and Packaging teams in chip closure and tape-out activities Experience/Requirements: + BSEE required, MSEE preferred with 2-3 years of experience in physical verification + Expertise with industry standard CAD tools (preferably Calibre) with strong emphasis in physical verification and tape-out + Hands-on experience in layout and sc...