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Cyient
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Analog Layout Engineer

Analog Layout Engineer

Cyient

3 - 5 years

15 - 22 Lacs

hyderabad

Posted:None| Platform:

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Skills Required

analog layout finfet 7nm cadence virtuoso high speed design

Work Mode

Hybrid

Job Type

Full Time

Job Description

Dear Analog Layout Engineers,

We, Cyient Semiconductor is hiring for Sr Analog Layout Engineers: High Speed: 7nm/ Lesser Exp for Offshore-Onshore Model based Global Product Solution from Scratch.

Exp Range: 3-5 Yrs

Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch

About the Role

Analog Mixed-Signal (AMS) Layout Engineer

Key Responsibilities

Perform
full-custom Analog layout design
for AMS circuits in advanced nodes (7nm or below).
Work on
FinFET device layouts
, ensuring compliance with
foundry-specific DRC/LVS
requirements.
Design
high-speed analog/mixed-signal blocks
such as SerDes, PLL, ADC/DAC, LDO, and other high-performance IPs.
Collaborate with circuit designers to understand schematic intent and translate it into optimized physical layouts.
Execute
layout parasitic extraction (PEX)
and work closely with verification teams for post-layout simulations.
Ensure
electromigration (EM), IR drop, and signal integrity
compliance in layouts.
Follow
design-for-manufacturability (DFM)
guidelines to maximize yield.
Debug and resolve LVS/DRC violations in advanced technology nodes.

Required Skills & Qualifications

Bachelors/Masters in Electronics, VLSI, or related field
.
3+ years
of relevant AMS layout experience (7nm or smaller preferred).
Proven expertise in
FinFET layout design
.
Experience with
high-speed analog/mixed-signal IPs
(SerDes, PLLs, ADC/DAC, PHYs).
Strong knowledge of
Cadence Virtuoso, Calibre, Assura
, or equivalent tools.
Familiarity with
PEX, LVS, DRC, ERC
verification flows.
Solid understanding of
layout-dependent effects (LDEs)
in advanced nodes.
Strong collaboration skills with designers and verification engineers.

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