Physical Design with Innovus Magnus Hr Consulting

7.0 - 12.0 years

32 - 47 Lacs

Bengaluru

Work from Office

Experience place & route flow, hierarchical design,Synthesis, Static Timing Analysis ,7nm, hierarchical designs

Posted 1 month ago

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LEC with Conformal LEC - Bangalore Magnus Hr Consulting

5.0 - 10.0 years

15 - 30 Lacs

Bengaluru

Work from Office

Develop and improve existing flow for logical equivalent check Experience with ABORT/NEQ debugging process Hands- on in logical equivalence tools such as Conformal LEC and/or Formality Understanding cross-functional RTL/PD/DFT teams Perl, Python, TCL

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Analog Layout Engineer Cyient

3.0 - 5.0 years

15 - 22 Lacs

hyderabad

Hybrid

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr Analog Layout Engineers: High Speed: 7nm/ Lesser Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 3-5 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking an Analog Mixed-Signal (AMS) Layout Engineer with deep expertise in 7nm or smaller process nodes , FinFET technologies , and high-speed layout design . The ideal candidate will have hands-on experience in complex analog, digital, and mixed-signal layouts, ensuring optimal performance, power, and area for cutting-edge semiconductor products. Key Responsibilities Perform full-custom Analog layout design for AMS circuits in advanced nodes (7nm or below). Work on FinFET device layouts , ensuring compliance with foundry-specific DRC/LVS requirements. Design high-speed analog/mixed-signal blocks such as SerDes, PLL, ADC/DAC, LDO, and other high-performance IPs. Collaborate with circuit designers to understand schematic intent and translate it into optimized physical layouts. Execute layout parasitic extraction (PEX) and work closely with verification teams for post-layout simulations. Ensure electromigration (EM), IR drop, and signal integrity compliance in layouts. Follow design-for-manufacturability (DFM) guidelines to maximize yield. Debug and resolve LVS/DRC violations in advanced technology nodes. Required Skills & Qualifications Bachelors/Masters in Electronics, VLSI, or related field . 3+ years of relevant AMS layout experience (7nm or smaller preferred). Proven expertise in FinFET layout design . Experience with high-speed analog/mixed-signal IPs (SerDes, PLLs, ADC/DAC, PHYs). Strong knowledge of Cadence Virtuoso, Calibre, Assura , or equivalent tools. Familiarity with PEX, LVS, DRC, ERC verification flows. Solid understanding of layout-dependent effects (LDEs) in advanced nodes. Strong collaboration skills with designers and verification engineers.

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