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Senior Memory Layout Engineer

Senior Memory Layout Engineer

Qualcomm

2 - 7 years

14 - 19 Lacs

bengaluru

Posted:None| Platform:

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Skills Required

physical verification cadence virtuoso drc debugging perl cmos mixed signal physical design vlsi design finfet lvs memory design cadence floorplan routing floor planning layout design ic design synopsys vlsi placement tcl analog layout

Work Mode

Work from Office

Job Type

Full Time

Job Description

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

2-5 years of experience in Custom layout and Memory Layout design.

Memory Leafcell layout library design from scratch including top level integration.

Good knowledge on different types of memory architectures and compilers

Good knowledge in optimized layout design for better performance.

Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout.

Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.

Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow

Proficient in SKILL and PERL for custom tiling and automations

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Senior Memory Layout Engineer