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DVE with 4+ years of experience. Immediate to 20 days notice period Bangalore WFH

Job Description Key Responsibilities – AMS Verification Work in Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Hands-on experience with AMS simulation environments using Cadence, Synopsys, or Mentor tools. Solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Strong knowledge of Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling. Experience in block-level and chip-level AMS verification, including top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective is a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation. Fluency with Cadence Virtuoso-based analog design flow, including schematic capture, simulator/netlist configuration, and SPICE simulation. Ability to extract, analyze, and document simulation results and present findings in technical reviews. Familiarity with test plan development, AMS modeling, and verification methodologies. Supporting post-silicon validation and correlating measurement data with simulations. Team-oriented, proactive, and able to contribute in a multi-site development environment.

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective will be considered a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation is required. You should be fluent with Cadence Virtuoso-based analog design flow, encompassing schematic capture, simulator/netlist configuration, and SPICE simulation. Your ability to extract, analyze, and document simulation results and present findings in technical reviews is highly valued. Furthermore, familiarity with test plan development, AMS modeling, and verification methodologies is essential. You will also be involved in supporting post-silicon validation and correlating measurement data with simulations. As a valued team member, you should be team-oriented, proactive, and able to contribute effectively in a multi-site development environment.,