Memory Layout Design Engineer - SRAM

- Good knowledge on different types of Memory architecture.
- Hands on experience on SRAM leafcell gds from scratch till top level integration.- Expertise in working on memory layout design for advanced nodes (TSMC : 7nm/5nm/3nm) is must.- Proficient in various physical verification flow debug, like DRC, LVS, DFM, PERC, ERC, EM, IR..- Proficient in Cadence virtuoso layout editor and caliber Physical verification flow.- Synopsys Custom compiler experience is huge plus.- Understanding and working knowledge of good layout practices in lower process nodes like 7nm and 5nm.- Expertise working on FinFET architecture and challenges such as variability and manufacturability- Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness- Expertise in performing debugging of silicon failures and identify layout-related issues- Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler- Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules- Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA)- Provide feedback on circuit designs to improve layout efficiency- Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits)- Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL)- Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations- Preferred resources with valid regional work permit.