19 Memory Layout Jobs

Role Overview: You will be responsible for designing analog mixed signal layout or memory layout for lower technology nodes in Germany, Bangalore, or Hyderabad locations. Key Responsibilities: - Designing analog mixed signal layout or memory layout for lower technology nodes - Collaborating with cross-functional teams to ensure successful project completion - Conducting layout verification and debugging to meet design specifications Qualification Required: - Bachelor's degree in Electrical Engineering or related field - 4-10 years of experience in analog mixed signal layout or memory layout - Proficiency in layout tools and techniques for lower technology nodes (Note: No additional details o...

We are looking for Memory Layout Engineers Exp: 10+yrs Loc: BLR Np: Immediate to 15 days If interested, please share your profile to my mail id sushma.vunnam@modernchipsolutions.com

Role Overview: You should have the ability to execute any small to mid-size customer project in VLSI Frontend, Backend, or Analog design with minimal supervision. Your role involves working as an individual contributor on tasks such as RTL Design/Module and providing support to junior engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your successful and on-time completion of assigned tasks will be crucial, with quality delivery approved by the project lead/manager. Key Responsibilities: - Work as an individual contributor on tasks such as RTL Design/Module and support junior engineers in various areas - Independe...

As a Memory Layout Lead at our company, you will play a crucial role in driving the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs including SRAM, ROM, register files, CAMs, and more. Your main responsibility will be to lead the end-to-end layout design and floorplanning for advanced-node memory IPs. Additionally, you will collaborate with circuit, CAD, and SoC integration teams to ensure optimal implementation. Your innovative layout techniques will be essential in achieving competitive density and performance targets. You will also be responsible for providing comprehensive IP deliverables such as GDSII, LEF, Liberty (.lib), Verilog m...

Years: 3yrs to 8yrs Location: Bangalore JD: 3-8 years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Good Knowledge in EM and IR run and fix. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Please share updated resume to madhuri.a.sivaraju@capgemini.com

Job Description for Memory Layout Location: Bangalore Experience 3yrs-10 Yrs - Memory leaf cell layout development - Migration of layout from one tech node to another - Block and top level integration - Quality and timely delivery - EM-IR, area intensive layouts, Quality checks (QC) - Understanding of design rules for 90nm and below - Understanding of design rules for 14ff and 16ff is a plus. - Drive multiple projects and provide necessary technical guidance to the engineers - Understanding of DFM and DFY - Understanding of memory compiler architectures - Good debugging skills - Knowledge of scripting in PERL/Shell/TCL scripting etc - Proficient with tools like Cadence Virtuoso, Calibre LVS ...

Key Responsibilities: Perform custom layout design of high-performance and low-power memory blocks (SRAM, ROM, Register Files, CAM, etc.). Work on floorplanning, transistor-level layout, device matching, and parasitic optimization. Ensure DRC/LVS clean layouts with adherence to foundry design rules. Collaborate with circuit design teams to achieve optimal PPA (Performance, Power, Area). Conduct parasitic extraction, EM/IR analysis, and reliability checks for memory layouts. Deliver high-quality layouts meeting project deadlines and silicon success. Required Skills: Strong expertise in memory layout (SRAM, ROM, CAM, Register Files). Hands-on experience with Cadence Virtuoso, Mentor Calibre, S...

- Good knowledge on different types of Memory architecture. - Hands on experience on SRAM leafcell gds from scratch till top level integration. - Expertise in working on memory layout design for advanced nodes (TSMC : 7nm/5nm/3nm) is must. - Proficient in various physical verification flow debug, like DRC, LVS, DFM, PERC, ERC, EM, IR.. - Proficient in Cadence virtuoso layout editor and caliber Physical verification flow. - Synopsys Custom compiler experience is huge plus. - Understanding and working knowledge of good layout practices in lower process nodes like 7nm and 5nm. - Expertise working on FinFET architecture and challenges such as variability and manufacturability - Expertise in work...

8+ years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch Knowledge on different types of memory architectures. Knowledge in optimized layout design for better performance. Knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug Proficient in Cadence Virtuoso layout editor and Calibre Interested can contact me at shubhanshi@incise.in

You will be responsible for memory layout design, including important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. Your hands-on experience should include working with 16nm/14nm/10nm/7nm/Finfet process technologies. You will be expected to have expertise in top-level memory integration, DRC, LVS, density verification, and cleaning physicals across the compiler space. It is essential to have a good understanding of IR/EM related issues in memory layouts and experience with Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A strong knowledge of ultra-deep sub-micron ...

We are looking for a Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, an...

We are looking for a Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, an...

You will be responsible for developing block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Your role will involve applying an understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues. It is essential to stay abreast of new verification methods and work collaboratively with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. To qualify for this posi...

Alternate Job Titles: Memory Design Engineer CMOS Memory R&D Engineer Embedded Memory Engineer Analog Circuit Engineer ASIC Memory Design Associate We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusiastic engineer who is passionate about memory design and eager to contribute to next-generation semiconductor techn...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their...

Role & responsibilities JD: Advanced memory layout design (SRAM, ROM, custom) Hands-on with FinFET, Virtuoso, Calibre, PVS Tight collaboration with circuit & verification teams Mastery in DRC/LVS, parasitic optimization, and layout efficiency Experience with foundry tech files and tapeout is a huge plus!

The role requires 3 to 8 years of experience in SRAM Memories layout design. You should be well-versed in various levels of memory layouts including custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, and decoders. Proficiency in floor planning, power planning, block area estimation of memory designs or compliers is essential. You must have expertise in leaf cell layout development and physical verification. Additionally, a good understanding of schematics, interface with circuit designer and CAD, and process development team is required. Strong knowledge of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, ma...

Role & responsibilities: Outline the day-to-day responsibilities for this role. Preferred candidate profile: Specify required role expertise, previous job experience, or relevant certifications.

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow