Role & responsibilities • 7 to 8-year experience in memory/analog/custom layout design in advanced CMOS process. • A strong understanding of memory design methodology and related issues is important. • The candidate should be well-versed in various levels of memory layouts, including custom memory bits, leaf cells, control blocks, read-write components, sense amplifiers, and decoders. • Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) • Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., • Ability to understand design constraints and implement high-quality layouts. • Excellent command and problem-solving skills in physical verification of custom layout. • Multiple Tape out support experience will be an added advantage. • Excellent verbal and written communication skills. Preferred candidate profile looking for Immediate Joiner Perks and benefits
