2.0 - 7.0 years

5 - 12 Lacs

Hyderabad, Bengaluru

Work from Office

Role & responsibilities JD: Advanced memory layout design (SRAM, ROM, custom) Hands-on with FinFET, Virtuoso, Calibre, PVS Tight collaboration with circuit & verification teams Mastery in DRC/LVS, parasitic optimization, and layout efficiency Experience with foundry tech files and tapeout is a huge plus!

Posted 2 weeks ago

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Associate III - VLSI ML UST Global

3.0 - 8.0 years

0 Lacs

karnataka

On-site

The role requires 3 to 8 years of experience in SRAM Memories layout design. You should be well-versed in various levels of memory layouts including custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, and decoders. Proficiency in floor planning, power planning, block area estimation of memory designs or compliers is essential. You must have expertise in leaf cell layout development and physical verification. Additionally, a good understanding of schematics, interface with circuit designer and CAD, and process development team is required. Strong knowledge of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. is necessary. Understanding layout effects on the circuit like speed, capacitance, power, and area is crucial. Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layout are expected. Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre is preferred. Leadership qualities and the ability to multitask are important. Working in a team environment, guiding, and providing technical support to team members are key responsibilities. Self-motivation, hard work, goal orientation, and excellent verbal and written communication skills are essential. Knowledge of Skill coding and layout automation is a plus. Responsibilities include Memory Compiler layout development and verification, Layout design and development of Memory blocks such as Array, Row/Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Performing layout verification like LVS/DRC/Latchup, quality check, and documentation. Ensuring on-time delivery of block-level layouts with acceptable quality. Demonstrating leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in a multiple project environment. Guiding junior team-members in their execution of Sub block-level layouts & reviewing their work. Contributing to effective project management and effectively communicating with engineering teams to assure project success. UST is a global digital transformation solutions provider that has been operating for over 20 years. UST partners with clients from design to operation, embedding innovation and agility into their organizations. With over 30,000 employees in 30 countries, UST aims to make a boundless impact touching billions of lives in the process.,

Posted 3 weeks ago

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Memory Layout Engineer Lancesoft

3.0 - 8.0 years

0 - 3 Lacs

Hyderabad, Bengaluru

Work from Office

Role & responsibilities: Outline the day-to-day responsibilities for this role. Preferred candidate profile: Specify required role expertise, previous job experience, or relevant certifications.

Posted 3 weeks ago

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Memory Layout Engineer : Bangalore Incise Infotech

3 - 5 years

20 - 35 Lacs

Bengaluru

Work from Office

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Posted 2 months ago

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