Job Description Position: DFT Lead Location: Bangalore, India Duration: Full Time Responsibilities: Responsible for writing timing constraints, running synthesis and implementing DFT (including scan, MBIST and IP testing), you will work on the company s next generation 5G IC and interact with software, signal processing algorithms, integration and layout teams. Requirements: At least 8 years experience of ASIC synthesis (including writing SDC), DFT (including scan and MBIST) and equivalence check, ideally with Cadence tools. Knowledge of CPF and Cadence CLP is a bonus. Highly motivated, pro-active self-starter. Strong sense of ownership and responsibility. Creative thinker with strong problem solving skills. Team oriented attitude and ability to thrive in a multicultural environment. Excellent written and oral communications skills. Qualifications: Bachelor s degree or higher in Computer Science or a related field. 8+ years of experience.
Job Description Position: IO Layout Engineer Location: Bangalore, India Duration: Full Time Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc. Knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E, 5nm etc. Skills: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Qualifications: Bachelor s degree or higher in Computer Science or a related field. 5 11 years of relevant experience.