Memory Layout Engineer (3-30 Years)

Company Description

SILCOSYS Solutions collaborates with clients in developing flagship product lines, including mobile devices, routers/switches, consumer goods, storage solutions, microprocessors, and graphics processors. The company pioneers cutting-edge technologies that are pivotal and rare in the industry. SILCOSYS Solutions is distinguished by its expertise in crafting intricate SoCs and boasts one of the industry's most robust analog/mixed signal and software design teams.

Position

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We are seeking an experienced Memory Layout Engineer with strong expertise in IC design, floor planning, and physical verification. The ideal candidate will have hands-on experience in Cadence Virtuoso and deep understanding of memory architecture, DRC/LVS, and EM/IR optimization.

Key Responsibilities:

• Develop and optimize memory layouts (SRAM, sense amplifiers, decoders, multiplexers, etc.)
• Perform DRC, LVS, ERC, and antenna checks using industry-standard tools
• Implement ECOs and design custom/mega cells for performance, power, and area optimization
• Collaborate with cross-functional teams to ensure design quality and tape-out readiness
• Conduct EM/IR analysis and apply layout optimization techniques

Requirements:

• 3+ years of experience in Memory Layout Design
• Proficiency in Cadence Virtuoso and Mentor Graphics Calibre

• Strong understanding of CMOS fundamentals, memory architecture, and layout best practices
• Familiarity with advanced nodes (2nm, 7nm, 12nm, 18nm) and foundry processes
• Good scripting knowledge (Linux, tcsh)

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