Memory Layout

Capgemini Technology Services India Limited

4 - 6 years

4 - 20 Lacs

bengaluru karnataka india

Posted:1 week ago| Platform: Foundit logo

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Skills Required

memory layout finfet drc/lvs/erc em/ir analysis cadence virtuoso calibre

Work Mode

On-site

Job Type

Full Time

Job Description

Experience:

46 years of experience in Memory or Custom Layout Design with strongexpertisein memory architectures and layout optimization techniques.

Responsibilities:

Design andoptimizememory layouts for high-performance and low-power applications.
Ensure compliance withFinFETtechnology requirements and DRC rules.
Perform physical verification flows (DRC, LVS, ERC) and debug issues effectively.
Conduct EM/IR analysis and implement necessary fixes.
Collaborate with circuit design teams to ensure layout accuracy and performance.
Automate layout processes using scripting languages for improved efficiency.

Technical Skills:

Strong understanding of memory architectures and layout optimization techniques.
Hands-on experience withFinFETtechnology and DRC rules.
Proficient in physical verification flows (DRC, LVS, ERC) and debugging.
Experience with EM/IR analysis and fixes.
Skilled in Cadence Virtuoso and Calibre tools.
Familiarity with scripting languages for automation and flow customization.

Preferred Skills:

Knowledge of advanced memory design methodologies.
Exposure to high-density memory layouts and low-power design techniques.
Strong problem-solving and analytical skills.

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