At Marvell, we lead the charge in cutting-edge technologies, including high-speed Ethernet Layer-1 connectivity for Data Centers. Our Layer-1 Platform team, spanning multiple geographies, is dedicated to making a long-term strategic impact on Marvell s Cloud Data Center offerings for AI enabled networks. This dynamic group is responsible for the software, firmware, and SDKs deployed in high-speed Data Center products that enable AI and support a vast range of market-deployed devices. As an engineer in this team, you will engage in all aspects of the Software Development Lifecycle, including Test Automation design, Test Automation development, Validation and Manual Test cases Execution Development. What You Can Expect Test Automation, Test cases Design, Test Automation development, new software/firmware features Test cases, Manual Test execution related to Bring-up, Layer-1 hardware (MAC, PCS, SerDes, PHY). Participate in design and architecture reviews for upcoming features and components. Perform in-depth SW/FW Validation, Automation, debugging of embedded software/firmware issues in complex next generation multi-processor systems. Collaborate with various teams across the company, including hardware SoC teams, hardware/software Development, internal customers, and field application engineers (FAE). Lead a team of SQA engineers What Were Looking For Bachelor s or Master s degree in Electrical , Electronics or Computer Engineering, or a related field with 10+ years of experience. Experience with networking protocols Experience with L1-L3 protocols and feature testing - Port, PoE, Vlan, routing, etc. Experience SDK/NOS testing Knowledge with configuration networking devices using API, SNMP, RestAPI - optional Experience with test equipment for testing as Xena, Spirent, Ixia or other software TG . Experience with detecting failures and debugging. Experience with testing workflows and methodologies. Automation development C, Python Experience with CI/CD Pipelines Communication English as a native language - read/write and daily communication. Technical Documentation - ability to read/create detailed technical documentation and test plans. Team Collaboration - experience working in agile teams and using collaboration tools like JIRA, Confluence, or similar. Soft Skills Problem-Solving Skills - Strong analytical and problem-solving abilities. Attention to Detail - High level of accuracy and attention to detail in testing and reporting. Management skills: Experience in leading teams of SQA engineers. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us
About Marvell . Your Team, Your Impact Working in Marvell automotive, you will be part of the fastest growing automotive ethernet business in the industry. Marvell is an established high quality, high integrity, customer centric automotive switch and PHY supplier that is enabling both combustion and electric vehicles in connectivity within the car infrastructure. The Automotive Ethernet Lab Technician supports the development and validation of Ethernet switch/PHY software. They manage test setups, execute validation protocols, and ensure compliance with automotive standards. What You Can Expect Test Environment Setup: Configure and maintain Ethernet switch/PHY test environments for software development and validation. Software Testing: Execute test cases for software and hardware integration, focusing on Ethernet performance and functionality. Data Analysis: Collect, analyze, and document test data to verify compliance with automotive standards. Equipment Maintenance: Calibrate and maintain lab equipment, including Ethernet switches, PHYs, and testing tools. Troubleshooting: Identify and resolve issues related to Ethernet switch/PHY performance during testing. Documentation: Maintain detailed records of test procedures, results, and any deviations or issues. Collaboration: Work closely with engineers and developers to refine tests and optimize software performance. What Were Looking For Qualifications: Education: Technical diploma or associate degree in electronics, electrical engineering, or related technical field. Technical Skills: Basic understanding of Ethernet, automotive networking, and test equipment. Familiarity with protocol analyzers, oscilloscopes, and network testers (preferred). Support Skills: Strong problem-solving and troubleshooting abilities. Communication: Good documentation skills and ability to follow instructions. Team Player: Willingness to support testing activities and collaborate with engineers. Preferred Experience: Previous experience supporting technical labs or testing environments. Exposure to automotive networking protocols (e. g. , Ethernet, CAN, LIN). Basic knowledge of lab safety and equipment maintenance. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell . Your Team, Your Impact This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for strong technical leaders in the domain of physical design having Full-Chip implementation experience on hierarchical designs using industry standard tools. #LI-LP1 What You Can Expect Should be able to independently handle every aspect of physical design. Should be able to direct junior engineers into execution Should be able to contribute to the overall development of the team What Were Looking For B-Tech/M-Tech candidate with 10+ years of hands-on experience and leadership in Physical Design. Should have played a PD lead role with 8+ years with experience in driving technical deliverables/dependencies across the design cycle (DFT/Timing/FE/Power). Candidate should have good experience in working on multi-million hierarchical designs, handling subsystem/partition physical implementation. Should have experience in working with global teams as a PD lead, demonstrating excellent problem solving skills on designs with latest technology nodes (10/7/5 nm). Candidate should possess excellent inter-personal skills with experience in providing mentorship to junior engineers, reviewing designs and providing technical guidance. Working knowledge of any scripting language PERL/TCL/AWK/Shell and having fluent written and oral communication skills is an added advantage #LI-MN1 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1
About Marvell . Your Team, Your Impact Marvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central Engineering AMS(CE AMS) is responsible of developing Marvell SerDes IPs and supporting all Marvell business units for fast and smooth SoC production. What You Can Expect IP verification activities - should have participated in successful completion of projects across all phases from Specification to Silicon Develop and execute verification plans using random techniques and coverage analysis. Create and maintain testbenches and test cases. Perform functional and performance verification. Debug and resolve design and verification issues. Collaborate with design and architecture teams to ensure verification coverage. Mentor junior engineers and lead verification projects. What Were Looking For Strong digital logic understanding and fundamentals of digital design. Excellent skills in complex IP verification using SV/UVM with proficiency in debug techniques Experience with simulation tools (e. g. , VCS) and knowledge of scripting languages (Python, Perl, TCL). Familiar with verification test planning and coverage driven verification closure, Verification strategies for directed and randomized testing and assertions Hands on verification experience on DDR/Ethernet/PCIe/CXL protocols Strong knowledge / experience in building the verification environment from specification and should have spec to hardware bring-up experience. Experience in leading projects to determine methods and procedures on new assignments and coordinate activities of other team members to ensure successful project completion. Strong analytical and problem-solving and analytical skills Ability to manage multiple tasks in a fast-paced environment Excellent communication, interpersonal, and teamwork skills Capable of interfacing effectively at all levels within and outside the organization Proactive in participating in problem-solving and quality improvement initiatives. Bachelor s degree in Computer Science, Electrical Engineering or related fields and 8-12 years of related professional experience Master s degree in Electrical Engineering with 8-10 years experience Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing. What Were Looking For Technical Requirement s: Bachelor s degree in CS/EE with 14 18 years of relevant experience, or Master degree in CS/EE with 12 16 years of relevant experience Must Lead a team of 4-6 engineers Experience in SOC/Subsys level/Block verification of ARM-based SOCs; experience in ARM based boot environment preferred. Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS, SVN, GIT etc. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell . Your Team, Your Impact At Marvell, we lead the charge in cutting-edge technologies, including high-speed Ethernet Layer-1 connectivity for Data Centers. Our Layer-1 Platform team, spanning multiple geographies, is dedicated to making a long-term strategic impact on Marvell s Cloud Data Center offerings for AI enabled networks. This dynamic group is responsible for the software, firmware, and SDKs deployed in high-speed Data Center products that enable AI and support a vast range of market-deployed devices. As an engineer in this team, you will engage in all aspects of the Software Development Lifecycle, including Test Automation design, Test Automation development, Validation and Manual Test cases Execution Development. What You Can Expect Test Automation, Test cases Design, Test Automation development, new software/firmware features Test cases, Manual Test execution related to Bring-up, Layer-1 hardware (MAC, PCS, SerDes, PHY). Participate in design and architecture reviews for upcoming features and components. Perform in-depth SW/FW Validation, Automation, debugging of embedded software/firmware issues in complex next generation multi-processor systems. Collaborate with various teams across the company, including hardware SoC teams, hardware/software Development, internal customers, and field application engineers (FAE). What Were Looking For Experience with networking protocols Experience with L1-L3 protocols and feature testing Port, PoE, Vlan, routing, etc. Experience SDK/NOS testing Knowledge with configuration networking devices using API, SNMP, RestAPI optional Experience with test equipment for testing as Xena, Spirent, Ixia or other software TG . Experience with detecting failures and debugging. Experience with testing workflows and methodologies. Automation development - C, Python Experience with CI/CD Pipelines Communication - English as a native language read/write and daily communication. Technical Documentation - ability to read/create detailed technical documentation and test plans. Team Collaboration - experience working in agile teams and using collaboration tools like JIRA, Confluence, or similar. Soft Skills: Problem-Solving Skills - Strong analytical and problem-solving abilities. Attention to Detail - High level of accuracy and attention to detail in testing and reporting. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1
About Marvell . Your Team, Your Impact As a Digital IC Design Senior Staff/Principal Engineer with Marvell, you ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You ll be playing a crucial role in establishing ESD requirements and validating ESD solutions for Foundational IP, SerDes IP, and SOCs during the ESD qualification process. You will work closely with the Physical Design, Electrical Engineering, and SOC (System on Chip) teams to provide support from the initial design phase through failure analysis, issue root cause determination, and the development of corrective actions. Being part of interface design team, you will have opportunities for the development of IO circuit to customer specifications including the generation and delivery of final EDA views for the IP. Typical circuits to be developed include biasing blocks, over-voltage/over-current protection circuits, regulators, amplifiers, switches, and a range of closed loop feedback circuits. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect Provide co-design support with both ESD simulations of circuits to maximize both performance and ESD protection robustness. Perform ESD design reviews and provide the required technical guidance for analog, foundational IP, SOCs, and qualification test chips for multiple technology nodes ranging from 45nm to 2nm across major foundry platforms. Validate and characterize ESD circuits using ICV PERC, Calibre PERC, TLP-based SPICE simulation, and any other industry methods and tools. Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools. Continue the development of best practices for ESD in the technologies being supported. Development and support of EDA tools for ESD design checking. Development of circuits like Driver, Receiver, Overvoltage protection circuits, Fail safe I/O, Bandgap and Voltage Regulators. What Were Looking For Bachelor s or Master s degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields and 8-15 years of related professional experience. Expertise in custom circuit design, handling layout effect in advanced FinFET process design rules, process variability and circuit reliability issues that affect power, speed, area, and yield. Advanced knowledge of on-chip ESD protection circuit design Advanced knowledge of CAD design tools such as Cadence and SPICE Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering. Advanced knowledge of ESD relevant device physics such as snapback and other high-level injection phenomenon/device operations Fully familiar with industry ESD test standards and latest developments. Experience with verifying ESD analysis for IP and SoC level using industry standard tools and methodologies. Exposure and experience with the Custom ESD PERC code development will have added advantage to this role. Experience with simulation skills using cadence including PEX, Monte Carlo, and Corner analysis. Derive design specifications from customer requirement. Requires effective communication between multiple sites and ability to work with multiple groups. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell . Your Team, Your Impact Marvell is a leading provider of innovative technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. The System software team (Firmware and Kernel) in the MBE BU focuses on developing and integrating key software components that enables use of Octeon series of silicons and custom silicons. These components form a critical subset of the complete software stack, ensuring the silicons capabilities are effectively utilized. The teams work plays a key role in supporting the broader software ecosystem. What You Can Expect In this position, you will be responsible for design, implementation and maintenance of Linux device drivers and debug utilities for ARM64 based SoCs. Participate in all phases of development and support including architecture, requirements, design, coding, unit testing, benchmarking, and support. Work closely with the Hardware, Firmware, and internal test teams on resolving issues during unit and integration testing. Contribute meaningfully to the Linux upstream community and OS distro vendors (such as RedHat and SUSE). What Were Looking For Bachelor s or Masters degree in computer science, Electrical Engineering or related fields with 4-18 years of related professional experience. Sound knowledge on ARM64 architecture. Strong working experience on Kernel internals, device driver development and virtualization concepts. Hands-on experience working on ARM trusted firmware (ATF). Knowledge on ARM64 debug and error handling technologies like RAS, synchronous/asynchronous errors, watchdog etc. will be a big plus. Excellent C programming skills. Excellent software design, problem-solving, debugging and documentation skills. Prior hands-on experience on using GDB, logic analyzer, Lauterbach is a plus. Excellent written and verbal communication skills with the ability to present complex technical information in a clear and concise manner to a variety of audiences. Ability to work independently with minimal guidance. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1
About Marvell . Your Team, Your Impact This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation on all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Candidate should have Physical Design experience in working on multi-million hierarchical designs, handling blocks as well as s ubsystem/par tition physical implementation. Should have experience in working with global teams, demonstrating excellent problem solving skills on designs with latest technology nodes (10/7/5 nm). Candidate should possess excellent inter-personal skills with experience in providing guidance to junior engineers through reviews as well as handling day to day technical deliverables. Working knowledge of any scripting language PERL/TCL/AWK/Shell and having fluent written and oral communication skills is an added advantage. What Were Looking For B-Tech/M-Tech candidate with 4-6 years of hands-on experience and leadership in Physical Design implementation. #LI-MN1 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1
About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications. What You Can Expect You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvells Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s Degree in Electrical/Computer Engineering or related fields and have 8+ years of related professional experience OR a Master s degree and/or PhD in Electrical/Computer Engineering, or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis. Good understanding of standard RTL to GDS flows and methodology Good scripting skills in languages such as Perl, tcl, and Python Good object-oriented programming skills Good understanding of digital logic and computer architecture Knowledge of Verilog/VHDL Good communication skills and self-discipline contributing in a team environment. #LI-MN1 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1
About Marvell . Your Team, Your Impact This position is with Power signoff team part of The Central Engineering PD group at Marvell, Bangalore. This team is part of global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for a strong technical individual contributor having experience in low power design using industry standard tools. What You Can Expect Work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design & Signoff Work on complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff Work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more. Collaborate with cross-functional teams including RTL design, verification, and DFT to optimize power. Perform floorplanning, placement, clock tree synthesis, routing, and physical verification. What Were Looking For Bachelor s or Masters degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Exposure on ASIC Physical implementation, Layout and Semiconductor device/process through previous work/intern experience or course work. Experience in power analysis, estimation, and optimization flow. Understanding of Physical Design and EM/IR flow Expertise in Tcl and PERL. Experience in Physical design is preferable. Scripting/programming using Tcl/Tk/Perl/Python/Shell Detail oriented, self-motivated team worker, good verbal, and written communication skills. Strong Digital Design concepts and debugging skills. #LI-MN1 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1
About Marvell Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Staff Engineer with Marvell, you ll be a member of the DCE business group. This group focuses on custom, compute and storage solutions of Marvell. With the increased focus on the security of the products you will be involved in helping steer the SDL vision into on-going and future SoCs being worked on in the group. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect As a Senior Staff Engineer, candidate will be responsible for developing verification plans and architecting test benches to validate DUT (Devise Under Test) functionality in simulation of application specific integrated circuit (ASIC/Integrated Circuit). Interpreting architectural and design requirements; Writing verification test plans and requirements; Developing and using complex test benches; Implementing directed and constrained random test cases; Collecting, analyzing, and enhancing functional and code coverage; Debugging issues in the requirements, tools, simulation environment, test cases, and DUT; Performing Object Oriented programming (System Verilog and C++); Participating in System Verilog Verification using a framework such as UVM or other industry standard methodologies; Verification automation and scripting using Perl/Shell/Python . What Were Looking For BS or MS (Electrical or Computer Engineering ) or Equivalent Degree with 10+ years of experience. Proficient with System Verilog, HDL languages, UVM , Object Oriented Programming and Scripting Languages. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is a leading provider of innovative technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets, providing complete solutions including controllers, product firmware, and reference board designs. Many of the same technologies have been utilized in Marvell system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect As a member of our team, you will work closely with architects and technologists to influence R&D in accelerated compute, networking, storage, and security technologies, including emerging low-latency transport protocols. Intelligently structure new feature designs and other software changes so that code is scalable, maintainable, and easily mergeable to legacy products as well as new products. Develop next-generation switching and DPU-based solutions tailored for enterprise and cloud-scale environments. Implement and optimize control plane and data plane functionalities for switch platforms and DPUs. Enhance Layer 2/3 networking capabilities including VLANs, VXLAN, L2GRE, MPLS, BGP, OSPF, and multicast for scalable, resilient infrastructure. Design and optimize high-performance switching fabrics with advanced packet processing, QoS, congestion control, and telemetry. Contribute to open-source initiatives (e.g., SONiC, SAI, OVS, DPDK, ODP, Linux kernel) and help define future networking standards. Collaborate with hardware teams to bring up new Switch SoC platforms and ensure seamless hardware-software integration. Participate in code reviews, design discussions, and continuous integration processes. What Were Looking For Bachelor s/Masters degree in Computer Science, Electrical Engineering, or a related field with 4 14 years of relevant experience. Proficiency in C, C++, Python, and Lua scripting. Deep understanding of Ethernet switching, Layer 2/3 protocols, DPUs, and networking standards. Understanding of RoCE, RDMA, and DPU concepts. Strong hands-on experience with SONiC, SAI, Cumulus Linux, OVS, DPDK, ODP, and DPU technologies. Familiarity with ARM multicore SoC architecture and high-speed packet I/O. Solid grasp of networking constructs such as ACLs, LPM, EM, routing, MAC learning, QoS, bridging, and load balancing. Exposure to cloud networking, SDN, or network virtualization technologies. Strong analytical and problem-solving abilities. Excellent communication and collaboration skills, especially in distributed team environments. Proven ability to independently plan, execute, and deliver complex technical projects. A passion for continuous learning and thriving in fast-paced, innovation-driven settings. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1
About Marvell Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Develop and maintain testbenches for IP, subsystem, and SoC-level verification Design and implement UVM-based verification environments Write and execute directed and random test cases Perform functional coverage analysis and debug failures Collaborate with design, architecture, and validation teams to ensure verification completeness Participate in code reviews, quality improvement, and problem-solving initiatives What Were Looking For - Bachelor s degree in CS/EE with 8 12 years of relevant experience, or Master s degree in CS/EE with 8 10 years of relevant experience - Strong background in IP, Subsystem and SoC verification, including methodology and testbench development - Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ - Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations - Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus - Strong analytical and problem-solving skills - Ability to manage multiple tasks in a fast-paced environment - Excellent communication, interpersonal, and teamwork skills - Capable of interfacing effectively at all levels within and outside the organization - Proactive in participating in problem-solving and quality improvement initiatives Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an individual contributor, you will be at the forefront of driving innovation in high-performance enterprise and cloud-scale networking. You will be responsible for developing advanced networking solutions using cutting-edge technologies such as DPU, Switch SoC, CXL, P4, SONiC, OVS, DPDK, ODP, and SAI. You ll work closely with cross-functional teams to enhance network programmability, security, and performance, while actively contributing to open-source communities and helping shape industry standards. What You Can Expect Bachelor s/Masters degree in Computer Science, Electrical Engineering, or a related field with 4 20 years of relevant experience. Proficiency in C, C++, Python, and Lua scripting. Deep understanding of Ethernet switching, Layer 2/3 protocols, DPUs, and networking standards. Understanding of RoCE, RDMA, and DPU concepts. Strong hands-on experience with SONiC, SAI, Cumulus Linux, OVS, DPDK, ODP, and DPU technologies. Familiarity with ARM multicore SoC architecture and high-speed packet I/O. Solid grasp of networking constructs such as ACLs, LPM, EM, routing, MAC learning, QoS, bridging, and load balancing. Exposure to cloud networking, SDN, or network virtualization technologies. Strong analytical and problem-solving abilities. Excellent communication and collaboration skills, especially in distributed team environments. Proven ability to independently plan, execute, and deliver complex technical projects. A passion for continuous learning and thriving in fast-paced, innovation-driven settings. What Were Looking For Develop next-generation switching and DPU-based solutions tailored for enterprise and cloud-scale environments. Implement and optimize control plane and data plane functionalities for switch platforms and DPUs. Enhance Layer 2/3 networking capabilities including VLANs, VXLAN, L2GRE, MPLS, BGP, OSPF, and multicast for scalable, resilient infrastructure. Design and optimize high-performance switching fabrics with advanced packet processing, QoS, congestion control, and telemetry. Build and integrate robust security features such as 802.1X, MACsec, NAC, micro-segmentation, and threat detection mechanisms. Contribute to open-source initiatives (e.g., SONiC, SAI, OVS, DPDK, ODP, Linux kernel) and help define future networking standards. Collaborate with hardware teams to bring up new Switch SoC platforms and ensure seamless hardware-software integration. Participate in code reviews, design discussions, and continuous integration processes. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1
About Marvell Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect - SOC & Sub system verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. - Responsible for complete SOC/Subsys verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. - Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. - Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. - Work effectively with a global team and be self-motivated to manage deliverables - Communicate clearly both verbally and in writing. What Were Looking For Bachelor s degree in CS/EE with 14 18 years of relevant experience, or Master s degree in CS/EE with 12 16 years of relevant experience - Experience in SOC/Subsys level (rather than block level) verification of ARM-based SOCs; experince in ARM based boot environment preferred. - Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. - Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. - Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. - Proficient in writing and debugging tests in UVM as well as C. - Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. - Experience with assertion-based formal verification tools. - Proficient in programming in scripting languages such as tcl and Perl. - Understanding of hardware emulation support. - Familiarity with TLMs in SystemC. - Experience in Version tools like CVS, SVN, GIT etc. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
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