Analog Mixed-Signal Verification Engineer

Job Overview:

GlobalFoundries is seeking a highly motivated Mixed-Signal Verification Engineer to join our advanced design team. In this role, you will be instrumental in verifying complex analog and mixed-signal IP blocks and subsystems using GlobalFoundries cutting-edge semiconductor processes. You will develop and execute comprehensive AMS verification plans, including behavioral modeling of analog components using Verilog-A/AMS and SystemVerilog. Your responsibilities will include building and maintaining mixed-signal testbenches, performing co-simulation using industry-standard tools such as Spectre, Xcelium, and AMS Designer, and automating regression testing and coverage analysis to ensure robust verification outcomes.

Additionally, you will work closely with layout and design teams to perform parasitic extraction (PEX) and post-layout simulation, ensuring layout-aware verification and accurate modeling of parasitic effects. This role requires a basic understanding of analog design principles, verification methodologies, and cross-domain collaboration to achieve high-quality deliverables

Essential Responsibilities :

• Develop and execute AMS verification plans for analog/mixed-signal Ips.
• Create behavioral models using Verilog-A/AMS and SystemVerilog.
• Build and maintain mixed-signal testbenches and perform co-simulation using industry-standard tools (Spectre, Xcelium, AMS Designer).
• Collaborate with design and layout teams to ensure verification coverage and post-silicon correlation.
• Automate regression testing and coverage analysis.
• Perform post-layout verification including parasitic extraction (PEX) and layout-aware simulation to ensure design robustness.
• Collaborate with layout and design teams to analyze parasitic effects and optimize performance across process corners.
• Utilize tools such as Calibre, Synopsys CustomSim, and Cadence Virtuoso for PEX extraction, LVS/DRC signoff, and post-layout simulation.

Required Qualifications :

• BS in Electrical Engineering or related field.
• 5+ years of experience in analog/mixed-signal verification.
• Proficiency in Cadence Virtuoso, Spectre, ADE-XL, SystemVerilog, Verilog-A/AMS.
• Strong understanding verification methodologies.
• Strong understanding of analog blocks and circuitsStrong collaboration skills to work with design and layout teams for performance optimization across process corners.
• Prior experience supporting memory macro designs (e.g., 55RRAM) is a plus

Preferred Qualifications:

• Hands-on experience with Cadence AMS Designer, Spectre, Xcelium, and Virtuoso for co-simulation and regression testing.
• Proficiency in creating behavioral models using Verilog-AMS, SystemVerilog real types, and mathematical abstractions.
• Experience with real-number modeling.
• Experience with silicon debug and post-silicon validation.
• Experience with parasitic extraction (PEX) tools such as Calibre xACT/xRC and/or Synopsys StarRC.
• Proficiency in post-layout simulation and layout-aware verification using Spectre and Virtuoso ADE-XL.
• Understanding of IR drop, and electromigration analysis.
• Familiarity with scripting languages (Python, Perl, Tcl).
• Strong communication and teamwork skills to work effectively across analog, digital, and layout teams.