33 Virtuoso Jobs

You will be involved in the design and development of high speed interface / high speed serial links (HSL) circuits upto 10 Gbps, PCIe Gen4, USB 3.1 Gen2/Gen1, MPHY, MIPI, IOs & LVDS. You will be responsible for PLLs/DPLLs/ADC design. Knowledge of analog circuit design and intuition is important. You should be able to coordinate the circuit design teams and the logic design teams. Ability to lead a team and work towards product delivery. Experience of Layout and IC fabrication will be preferable. Knowledge of SerDesis preferable. Excellent verbal and written communication skills. Working knowledge in the technology nodes of 65, 45, 28nm is preferred. The job function demands for the deep understanding on the protocols like USB, PCIE, MIPI, JEDEC, I2C, SPI etc. Mandatory Skills High Speed Circuit design Education Qualification Ph.D in VLSI/Microelectronics 0-3+ years of experience in verification of analog mixed signal blocks.Hands on tool expertise Cadence Suite:Virtuoso, AMS tools, Verilog, VerilogA and VAMS languages Mentor Suite: Calibre

Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Cadence Virtuoso, Spectre, or AMS Designer.

Responsibilities: * Ensure physical verification with Caliber and LVS tools * Collaborate on layout planning and execution using Virtuoso software * Perform DRC checks for design compliance Annual bonus

Responsibilities: * Create detailed layout designs using Virtuoso software. * Perform physical verification through DRC, LVS, ESD checks. * Collaborate with cross-functional teams on floor planning and antenna integration. Annual bonus

Job Description Potential candidate has to efficiently executes business strategies that are in line with organisational objectives. He/She also coordinates with channel partners to identify regional market opportunities, and builds working relationships amongst a diverse range of customers. Must have experience in field of sales and marketing of Fa ade systems. Experience of specifying products and handling projects with big customers / Builders / consultants and Architects. Potential candidate must have proven record of preparing and executing a Business plan in similar capacity to achieve desired target. Must have knowledge of Development cycle of a Fa ade system. Technically sound about different Fa ade systems.

About the Role: We are seeking a highly skilled and experienced Analog Layout Manager to lead our layout engineering team in the development of cutting-edge analog and mixed-signal ICs. This role requires deep technical expertise in analog layout, strong leadership capabilities, and the ability to deliver high-quality silicon in aggressive timelines. Key Responsibilities: Lead and manage a team of analog layout engineers to deliver high-quality layouts for analog and mixed-signal IPs (e.g., ADCs, DACs, PLLs, LDOs, PMICs, etc.) Own the floor planning, partitioning, and layout strategy for complex blocks and full chip integration. Collaborate closely with circuit design, verification, and physical design teams to optimize layout for performance, area, and reliability. Ensure adherence to foundry DRC/LVS/ANT/ERC/ESD guidelines and support closure of physical verification issues. Drive layout automation and CAD tool flows to improve efficiency and quality. Conduct design reviews and provide mentorship to junior layout engineers. Manage project schedules, resource planning, and risk mitigation strategies. Interface with external stakeholders including foundry, EDA vendors, and cross-functional teams. Required Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, or related field. 8+ years of hands-on experience in analog layout and team management. Proven track record of delivering production-quality analog/mixed-signal layouts in advanced nodes (e.g., 28nm, 16nm, 7nm, or FinFET technologies). Strong knowledge of parasitic extraction, EM/IR analysis, and layout-dependent effects (LDE). Proficient in layout tools such as Cadence Virtuoso, Calibre, Assura, and Mentor Graphics. Experience in team leadership, mentoring, and performance management. Excellent communication, documentation, and project management skills. Preferred Skills: Prior experience working in a fabless semiconductor environment. Knowledge of ESD protection, latch-up rules, and analog reliability concerns. Exposure to automotive, medical, or other high-reliability standards is a plus. What We Offer: Competitive compensation and benefits. Opportunity to work on leading-edge semiconductor technology. Collaborative and inclusive work environment. Professional development and career growth. Interested candidates can share their resumes to shubhanshi@incise.in

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. JD for CIC Frontend req AE3 Your role will be to meet customers/prospects and identify & qualify the opportunities, work out agreeable and achievable evaluation criteria, run through the evaluation and convert the opportunities into business leading to deployment of an efficient circuit simulation and mixed signal methodology using Cadence tools. It requires a very good understanding of customer flow & challenges and a good analytical ability to resolve issues impacting production schedule. Hands-on knowledge / experience on analog and mixed-signal circuit Design / Debug / modeling and simulation, would be a plus. The role demands a close interaction with R&D and Product Engineering team for implementation of new features and bug fixes. As the job requires an extensive interaction with customers for issue resolution and identifying opportunities to proliferate Cadence technologies, at the same time a closer interaction with R&D and other stakeholders, it demands an excellent customer and communication skills, and the leadership qualities. This position requires a solid understanding of IC design process/methodology in analog and mixed-signal design. The candidate should have in-depth knowledge and hands-on experience of complete analog front-end flow from design entry, real number modeling, pre-layout simulation, post layout simulation, mixed-signal simulation, EMIR analysis etc. with proficiency in tools like Virtuoso Schematic, Virtuoso ADE, Spectre, AMS Designer, etc. - B. Tech or equivalent with 3 to 7 years of relevant experience. We re doing work that matters. Help us solve what others can t.

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Layout concepts: Good knowledge in layout matching techniques and it usage Able to do floorplan, placement , routing and lvs-drc clean at block level Hands on experience in OPAMP , LDO, BGA and reference generate blocks Handle the block independently and able to communicate with design team Expertise in EM and IR fixes Good knowledge in floor planning of IPs like RX, TX and Synth IPs Understanding of DRC errors and fixing it including density errors . Good knowledge in Tsmc 6nm technology node Interested candidates can share their resumes to shubhanshi@incise.in

www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Message About the job Analog Layout Design Lead with 7+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Calibre) Ability to recognize and correct problematic circuit and layout structures Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected Ability to closely and independently work with Analog Designers to solve performance and area challenges Traits: Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills Adaptable, Flexible, Global Approach/Synthesis, Creative Willing to work on customer site for deployment and support Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.Sevyamultimedia.com Layout Senior Manager/ Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO PDK, Design Automation DRC/LVS/Extraction Rule deck Development PCell Development Automation Tools in Perl, Python, GoLang Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Location: Hyderabad #### **Job Summary:** We are seeking an experienced and dynamic Layout Design Manager to lead our layout design team. The ideal candidate will have a strong background in analog-on-top chip layout for devices with high-speed IO and analog components, as well as experience in dealing with ESD/latch-up issues, bump matrix design, RDL routing, power distribution, and critical signal planning. This role requires excellent leadership skills, the ability to manage complex design projects, and a strong technical background in layout design. #### **Key Responsibilities:** - **Team Leadership:** - Lead, mentor, and manage a team of layout design engineers. - Foster a collaborative and innovative team environment. - Develop team skills through training and professional development initiatives. - **Project Management:** - Plan and estimate layout design tasks, resources, and schedules. - Track and report on project progress, ensuring timely delivery of milestones. - Coordinate with cross-functional teams, including design, verification, and packaging, to align layout design activities with project goals. - **Analog-on-Top Layout Design:** - Oversee the layout design of analog-on-top chips with high-speed IO and analog components. - Ensure designs meet performance, power, area, and manufacturability requirements. - Optimize layout for ESD and latch-up prevention, signal integrity, and noise immunity. - **Bump Matrix and RDL Routing:** - Manage the design of bump matrix and redistribution layer (RDL) routing for advanced packaging. - Ensure efficient power distribution and critical signal planning. - **ESD/Latch-Up and Power Distribution:** - Address and resolve ESD and latch-up issues in layout designs. - Design robust power distribution networks to ensure reliable chip operation. - **Critical Signal Planning:** - Plan and implement critical signal routing to minimize interference and maximize performance. - Optimize layout for signal integrity and timing closure. - **Hiring and Training:** - Participate in the hiring process to recruit top talent for the layout design team. - Provide training and mentorship to new hires and junior engineers. - **Continuous Improvement:** - Stay updated with the latest industry trends, tools, and methodologies in layout design. - Drive continuous improvement initiatives to enhance design processes and methodologies. - Implement best practices for layout design and contribute to the development of standards and processes. #### **Qualifications:** - **Education:** - Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - **Experience:** - 10-15 years of experience in layout design, with at least 3 years in a managerial or leadership role. - Proven experience in analog-on-top chip layout for high-speed IO and analog devices. - **Technical Skills:** - Extensive experience with ESD and latch-up prevention techniques. - Proficiency in bump matrix design and RDL routing. - Strong knowledge of power distribution networks and critical signal planning. - Familiarity with CAD tools (e.g., Cadence Virtuoso, Mentor Graphics) for layout design. - Experience with physical verification (DRC, LVS) and parasitic extraction. - **Soft Skills:** - Excellent leadership and team management abilities. - Strong problem-solving and analytical skills. - Effective communication and interpersonal skills. - Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously. #### **Preferred Qualifications:** - Experience with advanced node technologies (e.g., FinFET, SOI). - Knowledge of reliability testing and failure analysis for analog and high-speed IO circuits. - Familiarity with scripting languages (e.g., Python, Perl) for automation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Message About the job Analog Layout Design engineer with 3-7+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Calibre) Ability to recognize and correct problematic circuit and layout structures Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected Ability to closely and independently work with Analog Designers to solve performance and area challenges Traits: Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills Adaptable, Flexible, Global Approach/Synthesis, Creative Willing to work on customer site for deployment and support Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We are seeking a skilled QA Engineer with strong experience in Salesforce (SFDC) migration testing. The ideal candidate will have expertise in testing automation and manual testing with a focus on data integrity, security, and API functionality. The role requires close collaboration with cross-functional teams including business stakeholders and project managers to ensure successful project delivery. Key Responsibilities: Conduct migration testing with a focus on Salesforce (SFDC) platforms. Perform automation testing using tools such as Virtuoso. Validate data integrity during and after migrations, ensuring accuracy and consistency. Perform API testing to validate data exchange between systems. Conduct data validation and data integrity testing for migrated data. Test permissions and security settings to ensure appropriate access controls. Collaborate with business users, project managers, and developers to gather requirements and create detailed test documentation. Ensure thorough test coverage by creating and executing comprehensive test plans and test cases. Maintain and manage test environments, troubleshooting issues as they arise. Document test results, defects, and issues, and communicate findings with stakeholders. Preferred Skills: Experience with Virtuoso . Strong analytical and problem-solving skills. Ability to manage multiple tasks and projects efficiently. Please share your resume to career@blackpiano.studio

Perform Salesforce (SFDC) migration & data integrity testing Execute automated tests , Virtuoso Conduct API testing & validate system integrations test plans, cases, & reports Create & manage detailed test plans, cases, and report.

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Qualifications:- BTECH/MTECH Location: Bangalore & Noida Experience:- The Engineers with 5 to 10 years of Experience 2.Job description - Physical Verification- Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 5 to 10 years of Experience Location:- Bangalore/ Noida

Role Proficiency: Ensuring adherence to test practices and process to improve test coverage Outcomes: Create Test Estimates and Schedules Identify business processes conduct risk analysis and ensure test coverage Ensure adherence of processes and standards Produce test results defect reports test logs and reports for evidence of testing Publish RCA reports and preventive measures Report progress of testing Contribute for Revenue savings for client by suggesting alternate method Quality of Deliverables Measures of Outcomes: Test Script Creation and Execution Productivity Defect Leakage Metrics (% of defect leaked % of UAT defects and % of Production defects) % of Test case reuse Test execution Coverage Defect Acceptance Ratio Test Review efficiency Outputs Expected: Test Design Development Execution: Participate in review walkthrough demo and obtain sign off by stakeholder for Test Design Prepare Test summary report for modules/features Requirements Management: Analyse Prioritize Identify Gaps and create workflow diagrams based on Requirements/User stories Manage Project: Participate in Test management Domain relevance: Identify business processes conduct risk analysis and ensure test coverage Estimate: Prepare Estimate Schedule Identify dependencies Knowledge Management: Consume Contribute Review (Best Practices Lesson learned Retrospective) Test Design Execution: Test Plan preparation Test Case/Script Creation Test Execution Test & Defect Management: Conduct root cause and trend analysis of the defects Test Planning: Identify the test scenarios with understanding of systems interfaces and application Identify end-to-end business critical scenarios with minimal support Create/Review the test scenarios and prepare RTM Skill Examples: Ability to create and manage a test plan Ability to prepare schedules based on estimates Ability to track and report progress Ability to identify test scenarios and prepare RTM Ability to analyse requirement/user stories and prioritize testing Ability to carry out RCA Ability to capture and report metrics Knowledge Examples: Knowledge of Estimation techniques Knowledge of Testing standards Knowledge of identifying the scope of testing Knowledge of RCA Techniques Knowledge of Test design techniques Knowledge of Test methodologies Additional Comments: Collaborate with Agile teams to analyze and clarify requirements. Create and maintain a Test Traceability Matrix to ensure coverage. Conduct thorough test analyses to identify scenarios and edge cases. Plan and prepare comprehensive test data for various test environments. Execute tests for both manual and automated scenarios. Perform database testing across multiple systems including SQL, Oracle, and MongoDB. Conduct browser-based testing across IE, Chrome, Edge, and Firefox to ensure compatibility. Perform API testing using tools like Virtuoso, Bruno, Postman, and Rest Assured. Work with Jira and Confluence for tracking and reporting test progress. Implement and maintain test automation frameworks for API testing. Conduct performance testing using jMeter to identify bottlenecks and optimize system performance. Integrate with CI/CD pipelines using tools such as Jenkins. Apply BDD practices with tools like Cucumber to ensure test scenarios align with business expectations. Maintain effective communication with stakeholders to report issues and test progress. Handson in AWS to make the automation scripts developed using AWS services and make the automation frameworks compatible to AWS Required Skills Automation Testing,Web Api Testing,Cucumber Framework,aws

• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. TSMC 3nm/5nm7nm/16nm Finfet & 3+ exp 3nm Provident fund Health insurance Annual bonus

As a Senior Network Engineer, you will be responsible for the design, implementation, integration, and optimization of complex network infrastructures. You will work on IP/MPLS networks, SDN, NFV, and cloud-based solutions to ensure high availability, security, and scalability. The role involves collaborating with cross-functional teams to deploy and maintain carrier-grade networking solutions for enterprise and service provider environments. You have: Proficiency in SDN and NFV concepts and technologies. Experience with E2E mobile solutions and mobile core systems. Design and implement cutting-edge virtualization solutions to enhance network performance. Hands-on experience with SDN, NFV, OpenFlow, and cloud networking. Drive the development of End-to-End mobile solutions, focusing on mobile and packet core architecture. Manage and optimize network management systems to ensure seamless connectivity and data flow. Analyze and troubleshoot network issues, providing innovative solutions to complex problems. It would be nice if you also had: Mentor junior team members and share knowledge on networking concepts and technologies. Familiarity with network management systems and advanced networking concepts. Certifications such as Nokia SRA/Virtuoso, Cisco CCIE, or Juniper JNCIE. Design and implement high-performance, scalable, and secure network architectures. Develop solutions for IP/MPLS backbone networks, SDN/NFV, and cloud-based networking. Conduct network capacity planning and recommend optimizations for performance and scalability. Define network policies, routing strategies, and security protocols. Deploy and configure network equipment such as routers, switches, firewalls, and load balancers (e.g., Nokia, Cisco, Juniper). Perform network integration, migration, and upgrades with minimal disruption to services. Troubleshoot complex network issues related to BGP, MPLS, QoS, VPNs, multicast, and security.

We are seeking a skilled Analog Layout Engineer to join our team at Nsemi. In this role, you ll be responsible for designing and optimizing analog and mixed-signal IC layouts, ensuring high performance and reliability. Your expertise will involve layout creation, verification, and adherence to design rules and specifications. Ideal candidates will have strong experience with analog circuit design, proficient use of layout tools, and a keen eye for detail. Join us to work on cutting-edge projects and contribute to the advancement of semiconductor technology. Qualification Required: Typically requires minimum of 3+ years of experience in Analog Circuit Design Bachelors / Master Degree in E&E and E&C Strong communication & team work skills Roles And Responsibilities: Expert in Power Management including hands-on DC-DC Converter, other precision analog circuits like operational amplifiers, Band-gap references, POR, Current Limit circuits, LDO regulators, comparators, oscillators etc. Experience in transceiver design for high speed interface such as Serdes, highspeed,DDR, HBM, PCIe, USB3, JESD204, Experience in transceiver design for high speed interface such as PLL,CTLE, DFE, CDR,PCIe, USB3, JESD204 Candidate should have taken atleast one block from circuit design and should be guide layout engineers for closure. Strong competency in small signal analysis and various frequency compensation techniques. Understanding of chip level ESD/LU requirements. Top-level integration, Block-level verification across PVT, Statistical Mismatch & mixed signal Verification. Hands-on working with Tools - Virtuoso/Tanner for schematic/model design & verification. Work closely with the Layout engineer to get optimized IP layout. This involves managing IP planning. Experience with Silicon validation and debug process. Planning, managing full-chip execution with team. Advantage if candidate has experience with high-current designs and/or multi-phase operation switching regulators

As a Senior Network Integration Engineer at Nokia, you will play a crucial role in IP Network Integration, Migration, and Network Upgrades, ensuring seamless integration with existing customer infrastructures. Your expertise in configuring and deploying network equipment and services according to design specifications will directly impact our mission to deliver innovative solutions. You have: Bachelors or Master s degree in Electronics, Computer Science, Electrical Engineering, or a related field with 10- 20 years of experience. Experience including design, build, deployment, trouble-shooting & fault-finding, etc. Experience in designing and deploying networking equipment, SDN and NFV products & technologies Experience with carrier networking protocols (BGP/MPLS/etc), VPNs, QoS, Multicast, Security, etc. Experience deploying KVM, VMWare, OpenStack or CloudStack, OpenFlow It would be nice if you also had: Nokia SRA/Virtuoso, Cisco CCIE, Juniper JNCIE, or equivalent Certification are a plus. Detailed understanding of IP/MPLS concepts, related technologies, and protocols You will configure and deploy network equipment and services per design specifications to ensure optimal performance. You will conduct thorough testing of deployed services to guarantee functionality, security, and compliance with performance standards. You will offer technical support to customers during and post-deployment, ensuring a smooth transition and operation. You will maintain up-to-date documentation of network configurations, changes, and troubleshooting procedures for future reference. You will Implement robust security measures to safeguard network integrity and protect customer data effectively. You will monitor network performance and usage trends to proactively identify improvement opportunities and troubleshoot issues.

As a Senior Network Integration Engineer, you will be responsible for the design, implementation, integration, and optimization of complex network infrastructures. You will work on IP/MPLS networks, SDN, NFV, and cloud-based solutions to ensure high availability, security, and scalability. The role involves collaborating with cross-functional teams to deploy and maintain carrier-grade networking solutions for enterprise and service provider environments. You have: Proficiency in SDN and NFV concepts and technologies. Experience with E2E mobile solutions and mobile core systems. Design and implement cutting-edge virtualization solutions to enhance network performance. Hands-on experience with SDN, NFV, OpenFlow, and cloud networking. Drive the development of End-to-End mobile solutions, focusing on mobile and packet core architecture. Manage and optimize network management systems to ensure seamless connectivity and data flow. Analyze and troubleshoot network issues, providing innovative solutions to complex problems. It would be nice if you also had: Mentor junior team members and share knowledge on networking concepts and technologies. Familiarity with network management systems and advanced networking concepts. Certifications such as Nokia SRA/Virtuoso, Cisco CCIE, or Juniper JNCIE. Design and implement high-performance, scalable, and secure network architectures. Develop solutions for IP/MPLS backbone networks, SDN/NFV, and cloud-based networking. Conduct network capacity planning and recommend optimizations for performance and scalability. Define network policies, routing strategies, and security protocols. Deploy and configure network equipment such as routers, switches, firewalls, and load balancers (e.g., Nokia, Cisco, Juniper). Perform network integration, migration, and upgrades with minimal disruption to services. Troubleshoot complex network issues related to BGP, MPLS, QoS, VPNs, multicast, and security.

Role & responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 5 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm/16nm Finfet & 5+ exp **** TSMC 3nm Exp - MANDATORY Preferred candidate profile Only Immediate Joiner Perks and benefits

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: Looking for an experienced technical writer with a solid technical background and impeccable communication skills to contribute to Virtuoso documentation. The candidate should preferably have an experience of 5-7 years in managing product documentation, release notes, videos, and blogs. Experience in DITA or any other topic-based authoring would be an added advantage. Job Responsibilities Understand electronic design automation (EDA) principles and related technical concepts, perform research, and translate the technical information into usable and practical product documents for consumption by Cadence customers. Work closely with subject-matter experts, including the development (R&D), product engineering, customer support, and product management teams, gain expertise in working hands-on with the EDA tools, and document new and enhanced software features, aligning with the release schedule. Understand and adhere to Cadence writing standards, develop topic-based (structured) content, and apply content taxonomy, and re-use strategies. Effectively use technical communications tools for authoring (FrameMaker, Wiki), screen capture/recording (SnagIT), video development (Captivate, Camtasia), and optionally graphic design (Photoshop). Coordinate with cross-functional teams in different geographies within Cadence and show a sound understanding of the product and documentation life cycle. Improve the product quality by reviewing product messages and UI. Develop supporting collateral, including feature videos and blogs. Experience A bachelors degree in any discipline (preferably computer science or electronics engineering) 4+ to 8 years of experience in a technical communications or instructional design role, preferably in EDA, semiconductor industry, or other technical domains. We re doing work that matters. Help us solve what others can t.

Develop/maintain DRC, LVS, RCX, Latchup rule decks and develop QA to meet high quality standards Develop new Pcells (symbol/layout) or enhance existing Pcells Work closely with the Design Teams, Technology Teams, and Fab groups to understand specifications and requirements Work closely with Technology department and Fab to define design rules and translate them into an accurate Calibre DRC and LVS rule decks Meet timelines and provide innovative solutions to achieve high level of satisfaction among PDK users Address change requests from the Device Design and Device Characterization groups in a consistent and effective way Demonstrate strong teamwork, communication skills and work ethics Respond effectively to design center/teams requests in a timely and consistent manner Develop and maintain component tests Your Profile You are best equipped for this task if you have: Familiar with full-custom and semi-custom design flows/design concepts Minimum 5+ years of relavent experience Expertise in developing PDK components - PV rule decks , Device libraries and techfiles Expertise in EDA tools (Calibre, Virtuoso, QRC) and their interfaces with PDK s Strong background in semiconductor device physics Strong layout and design verification experience including but not limited to Calibre: DRC, LVS, PERC, Assura QRC Good understanding of IC fabrication process and IC Design Process Good understanding of electronic circuits, layout techniques, Pcell usage and physical verification Expertise in programming/scripting languages w.r.t PDK development and QA Python, Perl, TCL, Cadence SKILL, Ruby Hands on experience with Configuration, Release and Build Management Exposure to issue tracking tools (JIRA) is a definite plus Exposure to formal QA procedures will be an added advantage Experience with MS-Office, ideally basic knowledge in working on UNIX/Linux platforms Excellent programming skills with computational thinking Proactive with good communication (assertive) and interpersonal skills Avid programmer with excellent debugging skills to diagnose and devise workarounds for PDK/flow/design issues