39 Virtuoso Jobs

As part of the custom product business at our company, you will be contributing to the development of industry-leading custom IC system solutions across various product categories such as display and touch power products, camera PMICs, charger power products, power switches/muxes, Laser drivers, and high-speed communication interfaces. By integrating signal chain and power components, your work will play a key role in enabling our customers to enhance their next-gen products in the personal electronics domain. Joining our team presents a unique opportunity to be part of a world-class custom semiconductor team. Your responsibilities in this role will include verifying complex analog designs/systems and providing support for the validation of designs on silicon. You will be responsible for releasing meticulously analyzed and simulated IC designs in a timely manner, ensuring they deliver optimal performance, cost-effectiveness, high quality, and meet our customers" end system requirements. Additionally, you will define, specify, model, plan, and implement the AMS verification strategy for mixed-signal ICs, including creating detailed verification plans and test cases, evaluating system-level use-cases, and contributing to post-layout parasitic extraction and simulation activities. To excel in this role, you are expected to have a strong background in defining and developing verification infrastructure for mixed-signal semiconductor products, along with a good understanding of analog circuits and expertise in tools such as Cadence Virtuoso, Cadence Spectre/TISpice, and Verilog-AMS/SystemVerilog. Proficiency in scripting languages like Python and Perl, as well as the ability to collaborate effectively with cross-functional teams, are essential skills for success in this position. Additionally, problem-solving abilities, strong communication skills, and the capacity to manage tasks independently with minimal supervision are key attributes we are looking for. With a minimum of 7 years of experience in mixed-signal verification and proficiency in tools like Virtuoso, Verilog, Verilog AMS, and Cadence tools such as xrun/ncsim/Vmanager, you will be well-equipped to meet the demands of this role. This position offers you the opportunity to work in a global organization, lead design and verification projects, and contribute to continuous improvements in design verification strategies, tools, methods, and flows. If you are passionate about shaping the future of electronics and seek a collaborative, innovative work environment, we invite you to apply for this exciting opportunity at our company. At Texas Instruments, we are committed to creating a better world through affordable electronics, and we value diversity and inclusivity in our workforce. Join us in engineering your future and being a part of our mission to drive innovation in the semiconductor industry. Please note that Texas Instruments is an equal opportunity employer and fosters a diverse and inclusive work environment. If you meet the qualifications outlined above and are interested in this position, we encourage you to apply.,

Data Converters (ADC/DAC) and PLL More Details Data Converters (ADC/DAC) and PLL AISEMICON As a Senior Analog/Mixed-Signal Design Engineer at AISemiCon, you will play a crucial role, focusing on high-performance analog- to-digital and digital-to-analog converters and PLL. The successful candidate in this role will do architecture, transistor level design starting from initial specification, through design and layout supervision. We are seeking individuals who have a strong passion for analog and mixed-signal design, possess deep expertise in Data Converters and PLLs, and thrive in solving complex challenges. The key responsibilities for this role include, but are not limited to: Responsibilities: High-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Collaborate with cross-functional teams to define and architect Data Converter (ADC/DAC) and PLL solutions for high-speed data acquisition and timing generation applications. Design and develop high-performance analog and mixed-signal circuits, including Data Converters and PLLs. Conduct transistor-level design, simulation, and layout of Data Converter and PLL blocks. Perform system-level verification and characterization of Data Converter and PLL designs, including performance analysis, noise analysis, and timing verification. Work closely with the system engineering team to ensure the Data Converter and PLL designs meet the performance requirements and specifications of the target applications. Drive innovation by exploring new techniques, circuit topologies, and emerging technologies in Data Converters and PLLs. Collaborate with customers and partners to understand their requirements and provide customized solutions. Provide technical guidance and mentorship to junior members of the team. Stay updated with the latest advancements in Data Converter and PLL design, industry standards, and emerging technologies. Qualifications: 5-7 years of experience in designing high performance building block circuits such as Bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc. Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools MATLAB understanding would be an added advantage Deep understanding of Data Converter architectures, analog-to-digital and digital-to-analog conversion techniques, and PLL principles. Proficiency in industry-standard EDA tools for IC design, simulation, and layout. Solid knowledge of system-level trade-offs and constraints in areas such as resolution, speed, power consumption, noise, and jitter. Experience with Data Converter and PLL characterization, validation, and debugging. Excellent problem-solving, analytical, and communication skills. Ability to work effectively in a collaborative team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. By using this form you agree with the storage and handling of your data by this website. *

We are looking for an experienced Analog Layout Engineer with 8+ years of hands-on experience in full custom layout of analog and mixed-signal blocks. The ideal candidate should have expertise in advanced CMOS technologies and be capable of delivering high-quality layout from specifications to tape-out. Key Responsibilities: Execute full custom layout for analog/mixed-signal blocks (OpAmps, Bandgaps, LDOs, ADCs, etc.) Floorplanning, device matching, parasitic optimization, and electromigration compliance Perform DRC/LVS/ERC checks and work closely with verification teams Collaborate with circuit designers to optimize performance and area Ensure quality layout delivery in accordance with tape-out schedules Support post-layout simulation and debug efforts Requirements: 8+ years of experience in analog/custom layout Strong understanding of matching, shielding, and analog layout best practices Hands-on experience with layout tools (Virtuoso, IC Compiler, Calibre, etc.) Knowledge of various technology nodes (180nm to FinFET) Good communication, teamwork, and problem-solving skills Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU s engineering team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As an SPE Signal Integrity Engineer, you will be reporting to the VP of Engineering and is a Full Time position. In this highly visible role, you will work within our SI/PI team to work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speed up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed Qualifications Solid background in SI/PI and package design to provide technical leadership to the team Strong interpersonal skill to keep the team motivated and focused MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5 Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required Solid theoretical background and understanding in EM and transmission line theory is a must Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc. Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations Proficient with simulations using Spice and ADS Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus Basic knowledge of circuits used in high-speed link design is preferred. Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams. Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player About Rambus With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for todays most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. The US- San Jose salary range for this full-time position is $141,500 to $281,000. Our salary ranges are determined by role, level and location. The successful candidate s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ . #LI-GL1

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads (TSMC 5nm preferred) with experience to join our growing team. Locations: Bangalore & Visakhapatnam. Notice Period : 30 days or less preferred. Job Description: Were seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests youor if you know someone suitableplease send your updated resume to: maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: Lead layout design activity and work with design team. Produce high quality IPs/AMS Blocks/Macros. Drive Area estimation, floor planning, placement, routing, power planning, verification, EMIR, ESD-LUP verification and tape out activity. Mentor Junior Analog IC Layout engineers. Develop scripts. You will be reporting to Director -Layout Design What youll need: Minimum 6 years of experience in Analog Layout. Minimum Education requirement is bachelors degree in electrical engineering. Understanding of low parasitic, high frequency design techniques. Excellent understanding of analog layout concepts and issues. Experience in handling blocks and macros layout towards successful, high-quality, and execution Experience with Finfet process and lower nodes like 2nm/3nm/5nm/7nm in TSMC foundry. Experience with multiple foundries in lower node eg: Samsung, TSMC, GF. Experience with Cadence tools (Virtuoso), Synopsys (CC), Calibre and ICV verification tools like LVS, DRC, Extraction etc. Experience with EMIR, PERC tools. Skill/TCL scripting experience. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

• Experience with EDA tools associated to Analog front-end from Cadence • Analog circuit design and simulations • Put in place new design/technology porting flows (using different EDA tools)

Lead the design, development, and verification of RF and analog IC blocks, including LNAs, mixers, power amplifiers, PLLs, VCOs, and ADC/DACs. Drive system architecture decisions for RF front-end and transceiver designs. Guide and mentor junior engineers, ensuring high-quality design practices. Perform top-level integration, ensuring seamless connectivity and performance of RF, analog, and mixed-signal circuits. Oversee simulation, layout reviews, and post-layout verification, optimizing for performance and manufacturability. Collaborate with layout, test, and product engineering teams for silicon validation and characterization. Define and execute design methodologies for efficiency, robustness, and first-pass success. Work closely with customers and cross-functional teams to define product specifications and roadmaps. Provide technical leadership in tape-out planning, foundry interactions, and process node selection. Requirements: 7+ years of experience in RF/analog IC design, with a track record of silicon success. Strong understanding of RF system design principles, including impedance matching, noise figure optimization, and linearity. Expertise in Cadence Virtuoso, Spectre RF, ADS, HFSS, and EMX. Deep knowledge of CMOS/BiCMOS technologies and layout-aware design methodologies. Experience in full-chip integration and packaging considerations for RF ICs. Hands-on experience with RF lab characterization and debugging. Strong leadership, mentorship, and project management skills. Excellent communication and ability to work in a fast-paced startup environment.

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.

We are looking for passionate and detail-oriented Analog or PCB Layout Design Interns to join design team. This is an excellent opportunity for engineering and diploma candidates to gain experience in real-world circuit design and PCB development. Analog Engineer Intern : Assist in designing analog circuits, including amplifiers, filters, power supplies, etc. Simulate analog circuits using tools such as LTSpice, PSpice, or Multisim. Participate in circuit debugging and validation on breadboards and PCBs. Work with engineers to improve circuit performance and reliability. Document schematics, simulation results, and testing procedures. PCB Layout Design Intern : Assist in schematic capture and PCB layout design using tools like Altium Designer, KiCad, Eagle, or OrCAD. Learn about PCB stack-up, trace width, clearance, and impedance control. Participate in Design Rule Checks (DRC) and Electrical Rule Checks (ERC). Support in preparing Gerber files and other manufacturing documents. Coordinate with hardware and manufacturing teams for PCB assembly and testing.

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Responsibilities: * Develop PLL/DLL designs using Virtuoso software * Collaborate with cross-functional teams on project requirements * Ensure compliance with industry standards and specifications Interested ,share resume to mansoor@hisoltech.com

Description: Description: Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 5 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm & 5+ exp **** TSMC Certification?Additional Details Target Rate : 0.00TSMC Certification? : YesShift : IND|1DAYH : Mon to Fri - 8 Hours - 9am to 6pmAccess Type : Account with Email

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: Lead layout design activity and work with design team. Produce high quality IPs/AMS Blocks/Macros. Drive Area estimation, floor planning, placement, routing, power planning, verification, EMIR, ESD-LUP verification and tape out activity. Mentor Junior Analog IC Layout engineers. Develop scripts. You will be reporting to Director -Layout Design What youll need: Minimum 6 years of experience in Analog Layout. Minimum Education requirement is bachelors degree in electrical engineering. Understanding of low parasitic, high frequency design techniques. Excellent understanding of analog layout concepts and issues. Experience in handling blocks and macros layout towards successful, high-quality, and execution Experience with Finfet process and lower nodes like 2nm/3nm/5nm/7nm in TSMC foundry. Experience with multiple foundries in lower node eg: Samsung, TSMC, GF. Experience with Cadence tools (Virtuoso), Synopsys (CC), Calibre and ICV verification tools like LVS, DRC, Extraction etc. Experience with EMIR, PERC tools. Skill/TCL scripting experience. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Experience: 3-5 years Notice period: immediate - 15 days Location: Hyderabad interview: 2-3 rounds Job Description: - Develop standard cell layouts and detailed drawings from schematics - Perform physical verification and layout optimization - Collaborate with design engineering and CAD teams - Ensure design rules, yield, and reliability requirements are met. - Expertise in Cadence tools, including Virtuoso and Caliber - Strong understanding of layout fundamentals and physical verification - Excellent problem-solving and communication skills.

Experience: 3-5 years Notice period: immediate - 15 days Location: Hyderabad Interview: 2-3 rounds Mandate Skills: Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, CMOS process, standard cell layout, analog, mixed-signal and custom digital block designs , Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber Interested Engineers can share their resumes at [HIDDEN TEXT] Note: matching profiles will get get Mail/Call from us.

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.

Required Qualifications: ? Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 4-20 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications:? Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English? Strong analytical and problem-solving skills.?

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 3 to 4 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout Schedule time-line & layout floor-planning Complete quality layout and verification within planned schedule (without supervision for experienced engineer) Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team Skill Set (Mem): Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, ElectroMigration in CMOS process. Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools. Good experience in Floor-planning, hierarchy layout and chip integration. Knowledge of Script Programming and SKILL Programming would be a plus. Able to lead or train a team of junior engineers Good knowledge on memory layout topology. Experience in the memory compiler will be a plus. Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines. Self-reliant, with ability to work independently as well as a team. Good leadership quality on project management. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

RF Circuit Design: Expertise in the design and simulation of RF circuits such as LNAs, mixers, power amplifiers, VCOs, and filters. Tools & Simulation: Proficient in using RF design tools (e.g., ADS, HFSS, Cadence Virtuoso) and simulation methodologies for RF circuits. Layout Considerations: Strong understanding of RF layout techniques, including impedance matching, parasitic extraction, and electromagnetic interference (EMI) Antenna Design: Experience in antenna design and integration within RF systems. System Integration: Knowledge of RF system architecture, including transceiver design and RF signal chain analysis. Test & Measurement: Skilled in using RF test equipment (e.g., spectrum analyzers, network analyzers) for design validation and characterization. Regulatory Compliance: Familiarity with RF compliance standards and regulatory requirements (e.g., FCC, ETSI). Expectations from the Role: Technical Expertise: Strong technical expertise in RF design principles and the ability to innovate within challenging design constraints. Collaboration: Excellent communication and collaboration skills, with the ability to work closely with cross-functional teams. Problem-Solving: Ability to diagnose and resolve complex RF issues through both simulation and lab measurements. Time Management: Ability to manage multiple projects simultaneously, ensuring timely delivery of high-quality designs. Leadership: Potential to lead and mentor junior engineers within the team.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 6 to 10 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout Schedule time-line layout floor-planning Complete quality layout and verification within planned schedule (without supervision for experienced engineer) Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team Skill Set (Mem): Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, ElectroMigration in CMOS process. Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools. Good experience in Floor-planning, hierarchy layout and chip integration. Knowledge of Script Programming and SKILL Programming would be a plus. Able to lead or train a team of junior engineers Good knowledge on memory layout topology. Experience in the memory compiler will be a plus. Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines. Self-reliant, with ability to work independently as well as a team. Good leadership quality on project management. .

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 3 to 4 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout Schedule time-line layout floor-planning Complete quality layout and verification within planned schedule (without supervision for experienced engineer) Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team Skill Set (Mem): Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, ElectroMigration in CMOS process. Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools. Good experience in Floor-planning, hierarchy layout and chip integration. Knowledge of Script Programming and SKILL Programming would be a plus. Able to lead or train a team of junior engineers Good knowledge on memory layout topology. Experience in the memory compiler will be a plus. Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines. Self-reliant, with ability to work independently as well as a team. Good leadership quality on project management. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 6 to 10 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout Schedule time-line layout floor-planning Complete quality layout and verification within planned schedule (without supervision for experienced engineer) Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team Skill Set (Mem): Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, ElectroMigration in CMOS process. Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools. Good experience in Floor-planning, hierarchy layout and chip integration. Knowledge of Script Programming and SKILL Programming would be a plus. Able to lead or train a team of junior engineers Good knowledge on memory layout topology. Experience in the memory compiler will be a plus. Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines. Self-reliant, with ability to work independently as well as a team. Good leadership quality on project management. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

You will be involved in the design and development of high speed interface / high speed serial links (HSL) circuits upto 10 Gbps, PCIe Gen4, USB 3.1 Gen2/Gen1, MPHY, MIPI, IOs & LVDS. You will be responsible for PLLs/DPLLs/ADC design. Knowledge of analog circuit design and intuition is important. You should be able to coordinate the circuit design teams and the logic design teams. Ability to lead a team and work towards product delivery. Experience of Layout and IC fabrication will be preferable. Knowledge of SerDesis preferable. Excellent verbal and written communication skills. Working knowledge in the technology nodes of 65, 45, 28nm is preferred. The job function demands for the deep understanding on the protocols like USB, PCIE, MIPI, JEDEC, I2C, SPI etc. Mandatory Skills High Speed Circuit design Education Qualification Ph.D in VLSI/Microelectronics 0-3+ years of experience in verification of analog mixed signal blocks.Hands on tool expertise Cadence Suite:Virtuoso, AMS tools, Verilog, VerilogA and VAMS languages Mentor Suite: Calibre

Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Cadence Virtuoso, Spectre, or AMS Designer.