Design Verification Senior Principal Engineer

Your Team, Your Impact

- Be part of the Design Verification team in DCE - CCS - Lead End-to-End SoC DV execution and sign-off - Define and drive improvements in DV processes for efficient and high-quality execution - Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews - Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure, and gate-level simulations - Coordinate with cross-functional teams including Architecture, Chip Lead, Emulation, and Program Management to drive SoC-level DV execution - Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities - Own and debug simulation failures to identify and resolve root causes - Architect and implement simulation testbenches using UVM & C. - Develop and execute test plans to verify design correctness and performance - Collaborate with logic designers for thorough verification coverage and closure

What You Can Expect

- Lead End-to-End SoC DV execution and sign-off
- Define and drive improvements in DV processes for efficient and high-quality execution - Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews - Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure, and gate-level simulations - Coordinate with cross-functional teams including Architecture, Chip Lead, Emulation, and Program Management to drive SoC-level DV execution - Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities - Own and debug simulation failures to identify and resolve root causes - Architect and implement simulation testbenches using UVM & C. - Develop and execute test plans to verify design correctness and performance - Collaborate with logic designers for thorough verification coverage and closure

What Were Looking For

Technical Expertise:
- Must have experience in SOC/Subsys/IP level verification of ARM-based SOC and experience in ARM boot sequences - Must have knowledge of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. - Experience with industry standard interfaces such as DDR, HBM, PCIE, Ethernet and USB. - Experience coding UVM SOC/Subsys/block level testbenches, BFM, scoreboards, monitors, etc. - Proficient in writing and debugging tests in UVM as well as C. - Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. - Experience with assertion-based formal verification tools. - Proficient in programming in scripting languages such as tcl and Perl. - Understanding of hardware emulation support. - Familiarity with TLMs in SystemC. - Experience in Version tools like CVS, SVN, GIT etc

Qualification & Experience:

- Bachelor s degree in CS/EE with 20+ years of relevant experience, or Master s degree in CS/EE with 18+ years of relevant experience
- Strong background in IP, Subsystem and SoC verification, including methodology and testbench development - Experienced in Leading a team of 6+ engineers & leads