4 Finfet Technology Jobs

Build your career with Sykatiya Technologies! Sykatiya Technologies values both technical ability and the attitude of its highly talented team, which is evident in their contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, as well as experience in FINFET technology and the 32G-112G range of SERDES. The successful candidate should have taken at least one block from circuit design to layout closure and be capable of guiding the layout team for high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, etc., is essential. The candidate should be able to work independently, mentor juniors, and have exposure to post-silicon validation. If you are a motivated Analog Design Engineer looking to work with a team of experts and contribute to cutting-edge projects, we encourage you to apply and be a part of our innovative team at Sykatiya Technologies.,

As an Analog Design Engineer at Sykatiya Technologies, you will be an integral part of our highly talented team that focuses on Technical Ability and a positive Attitude. Your contributions to projects will reflect our commitment to excellence for our customers. Our team consists of skilled engineers and experts in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, along with experience in FINFET technology and the 32G-112G range of SERDES. In this role, you will be responsible for taking at least one block from circuit design to layout closure. You should also be able to guide the layout team in high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, and being able to work independently while mentoring junior team members are essential qualities we are looking for. If you have exposure to post-silicon validation, it would be considered a plus. Join us at Sykatiya Technologies and be part of a dynamic team that values technical expertise, a positive attitude, and a commitment to excellence in Analog Design.,

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and motivated Physical Design Engineer with a passion for innovation and a proven track record in the semiconductor industry You thrive in dynamic environments and are adept at managing multiple projects simultaneously Your deep understanding of the full design cycle from RTL to GDSII, particularly in advanced FinFET nodes, positions you as a technical driver in your field You possess excellent communication skills, enabling you to effectively collaborate with cross-functional teams and stakeholders Your solid software and scripting skills, combined with your expertise in CAD automation methods, make you an invaluable asset to any project You are autonomous, capable of making timely judgments, and able to handle interruptions with ease, What Youll Be Doing: Driving the physical implementation of high-speed interface IPs and test-chips from SYN to GDS, Utilizing your software and scripting skills to enhance CAD automation methodology for the team Collaborating with multiple functional groups, including front-end, analog and CAD teams, Focusing on advanced SerDes developments, including the latest 112G/224G PAM4 standards, Leading the physical design team to ensure on-time delivery of projects, The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything, Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements, Reducing the risk and time-to-market for differentiated products, Driving technological innovation through advanced SerDes development, Enhancing Synopsys reputation as a leader in chip design and verification, Supporting the company's mission to power the worlds most advanced technologies for chip design and software security, What Youll Need: 10+ years of physical design experience with recent contributions to project tape-outs or IP delivery Strong tcl scripting skills in Place & Route Tools (Fusion Compiler / ICC2 / Others) Understand version control & have experience in one of the version control software (Perforce / Git / Svn / Clearcase) Experience with advanced FinFET nodes, TSMC 7 nanometer or below, Solid understanding of IC design, implementation flows, and methodologies for deep submicron design, Proven track record for technical steering of physical design teams for on-time delivery, Who You Are: Excellent communicator with the ability to engage with peer groups and customers, Autonomous and capable of making timely judgments, Proficient in software and scripting skills (Perl, Tcl, Python), Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs, Able to travel internationally as required, The Team Youll Be A Part Of: You will be part of a collaborative team within the Mixed-Signal IP organization, working closely with front-end, analog, and CAD teams The team focuses on the physical implementation of complex mixed-signal IPs and test-chips across multiple process technologies, with a specific emphasis on advanced high-speed SerDes platforms, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Responsibilities: - Manage and mentor a team of 8-10 senior analog designers focused on high-speed SerDes IP development across multiple projects - Define architecture specifications and circuit implementation requirements for next-generation SerDes PHY IPs - Ensure adherence to project schedules, quality metrics, power/area targets through effective team oversight - Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components - Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes - Continuously drive design methodology improvements and adoption of latest EDA tools/flows - Develop and manage operational plan, including staffing, budgets and resource allocation - Hire, develop and retain top analog engineering talent through active mentorship Requirements: - Bachelors degree in electrical engineering; advanced degree preferred -8+ years of experience in analog/mixed-signal IC design with a strong background in SerDes architectures - 2+ years of people management experience leading high-performance analog design teams - Proven expertise in high-speed I/O design, architectures, circuits, and layout implementation - Extensive knowledge of CDR, DFE, CTLE, EQ, decision feedback equalizer design techniques - Hands-on experience with analog/mixed-signal design flows, tools (Cadence, Synopsys), modeling - Understanding of FinFET transistor characteristics and design challenges at advanced nodes - Strong project management skills with the ability to manage multiple priorities - Excellent communication and people leadership abilities to motivate cross-functional teams