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Capgemini
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Static Timing Analysis Engineer

Static Timing Analysis Engineer

Capgemini

5 - 9 years

0 Lacs

coimbatore tamil nadu

Posted:3 days ago| Platform: Shine logo

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Skills Required

timing analysis closure synopsys primetime eda tools communication leadership mentoring cross functional coordination constraint development tool usage flow integration sta tools cadence tempus problemsolving design flow management

Work Mode

On-site

Job Type

Full Time

Job Description

At Capgemini Engineering, the world leader in engineering services, you will be part of a global team of engineers, scientists, and architects dedicated to helping innovative companies unleash their potential. Your role will involve providing unique R&D and engineering services across various industries, contributing to cutting-edge projects such as autonomous cars and life-saving robots. Join us for a career full of opportunities where you can make a difference every day. Key Responsibilities: - Timing Analysis & Closure - Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. - Achieve timing closure by resolving violations and optimizing paths. - Constraint Development - Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). - Integrate constraints from multiple IPs for hierarchical STA. - Tool Usage & Flow Integration - Use STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent. - Integrate STA into the overall design flow and automate processes for efficiency. - Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths for Full Chip, Sub-system, and complex IP timing closure. - Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints for Full-Chip, Sub-system to ensure accurate timing analysis. - Able to integrate existing timing constraints from various IPs for Full-Chip/Sub-system timing analysis. - Deep knowledge of STA tools (such as Synopsys PrimeTime, Cadence Tempus, or Mentor Graphics" ModelSim) including their capabilities, limitations, and best practices. - Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance. - Oversee the process of achieving timing closure, addressing any timing violations, and guiding optimizations to meet performance goals. Primary Skills: - Deep Technical Knowledge: - In-depth understanding of STA concepts, EDA tools, and methodologies. - Experience in timing constraints development, timing closure for Full-Chip/Sub-system to meet the design performance. - Problem-Solving Skills: Strong analytical and problem-solving abilities to tackle complex timing issues. - Communication Skills: Ability to communicate complex technical concepts effectively to various stakeholders. - Leadership and Mentoring: Experience in leading teams and mentoring less experienced engineers in STA practice. Secondary skills: - Design flow management - Able to improve the execution efficiency through flow automation and other value adds. - Cross-functional co-ordination - Work closely with other teams, such as RTL design, Physical design, design, verification, and manufacturing, to ensure seamless timing closure of physical design. Educational Qualifications: - Bachelors or Masters Degree in: Electrical Engineering/Electronics & Communication Engineering/VLSI Design/Computer Engineering or related fields Capgemini is a global business and technology transformation partner, trusted by clients worldwide for over 55 years. With a team of 340,000 members in more than 50 countries, Capgemini delivers end-to-end services and solutions leveraging strengths in AI, cloud, and data. The company is committed to unlocking the value of technology to address diverse business needs, contributing to a digital and sustainable world while creating tangible impact for enterprises and society.,

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Static Timing Analysis Engineer