3 Synopsys Primetime Jobs

As an engineer at Synopsys, you will be a key player in driving innovations that shape the future of technology. Your role will involve working with cutting-edge tools and technologies to ensure the high quality and reliability of Synopsys's PrimeTime tool. You will collaborate with cross-functional teams to tackle complex technical challenges and provide valuable insights that influence the development and validation of future product releases. Your primary responsibilities will include executing and leading product validation of the PrimeTime tool, understanding requirements and functional specifications, and performing in-depth root cause analysis to enhance product quality. You will use your expertise in Static Timing Analysis (STA) and tools like Synopsys PrimeTime to diagnose issues, propose innovative solutions, and ensure the readiness of the product for customer deployment. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python will enable you to streamline processes and improve efficiency. In this role, you will have a significant impact on enhancing customer satisfaction, driving continuous improvements in product design, and contributing to the overall success of Synopsys. You will play a crucial part in deploying cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. Your attention to detail, analytical thinking, and problem-solving mindset will be key to maintaining high standards of product quality and reliability. To excel in this role, you should have deep domain knowledge in Static Timing Analysis, a Bachelor's or Master's degree in Electrical Engineering or equivalent, and a minimum of 3-5 years of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, power, SDC constraints, and scripting skills are essential. As a collaborative team player with excellent communication skills, a proactive and self-motivated individual, and someone who thrives in a fast-paced environment, you will be a valuable addition to the product validation team for Synopsys's PrimeTime tool. Join us at Synopsys to transform the future through continuous technological innovation and be part of a team dedicated to ensuring the high quality of tools that drive the semiconductor industry forward.,

NVIDIA is continuously reinventing itself, with a rich history that includes inventing the GPU, which sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. The current global boom in artificial intelligence research demands highly scalable and massively parallel computation horsepower, a challenge where NVIDIA GPUs excel. As a part of NVIDIA, you will be joining a dynamic team focused on tackling difficult global challenges and amplifying human creativity and intelligence. The diverse and supportive environment at NVIDIA encourages everyone to strive for excellence and make a lasting impact on the world. NVIDIA is seeking a talented ASIC STA Engineer to join the Networking Silicon engineering team. In this role, you will contribute to the development of high-speed communication devices, ensuring the highest throughput and lowest latency for AI platforms. You will work on designing innovative large-scale chips and collaborate in a professional environment where your contributions matter. Key Responsibilities: - Lead full chip and/or chiplet level STA convergence from initial stages to signoff. - Contribute to top-level floor plan and clock planning. - Optimize CAD signoff flows and methodologies. - Integrate digital partitions and analog IPs timing, provide feedback to PD/RTL, and drive convergence. - Collaborate closely with logic design and DFT engineers to define and implement constraints for various work modes efficiently. Requirements: - B.Sc./M.Sc. in Electrical Engineering/Computer Engineering. - 3-8 years of experience in physical design and STA. - Proven expertise in RTL2GDS and STA design and convergence. - Familiarity with physical design EDA tools (e.g., Synopsys, Cadence). - Hands-on experience with STA using Synopsis Primetime. - Strong understanding of timing concepts and a collaborative team player. At NVIDIA, we have a team of forward-thinking individuals who are passionate about pushing boundaries. If you are a creative engineer who enjoys challenges and is ready to grow professionally, come be a part of our industry-leading physical design team. JR1995153,

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurturing their technical growth and promoting knowledge sharing within subsystem teams. Collaboration with various cross-functional teams will be essential to resolve design, timing, and physical implementation challenges that are specific to the integration of complex subsystems. Your qualifications should include a minimum of 10 years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, with expertise in advanced technology nodes such as 7nm or below. Proficiency in STA tools like Synopsys PrimeTime, Cadence Tempus, and PNR tools such as Synopsys ICC2, Cadence Innovus for application in large, multi-block, or hierarchical subsystems is required. A proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be skilled in scripting languages like Tcl, Perl, Python for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience in collaborating across frontend, physical design, and verification teams to integrate complex subsystems are crucial. Previous experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level would be advantageous. A background in high-speed interfaces or mixed-signal SoC subsystems is preferred for this role.,