25 Synopsys Primetime Jobs

Job Summary We are seeking a highly skilled and experienced Principle/Staff STA Engineer to join our dynamic team in Noida. This role involves leading and executing Static Timing Analysis (STA) for complex SoC designs, ensuring timing closure, and contributing to the development of next-generation semiconductor products. Job Responsibilities Lead and perform comprehensive Static Timing Analysis (STA) at the block, sub-system, and SoC levels for cutting-edge semiconductor designs. Develop, integrate, and maintain timing constraints (SDC) for various design hierarchies, ensuring accuracy and coverage. Identify, debug, and resolve complex timing violations, including setup, hold, and other adva...

JD for a Physical Design Lead (Sub-3 nm, TSMC, 810 yrs, Synopsys / Cadence) Job Title Physical Design Lead Advanced Node (Sub-3 nm, TSMC) Location: Bangalore Experience : 8+ to 12 years Job Mode : Full Time Position Summary Lead end-to-end physical implementation and signoff for complex SoC blocks or subsystems at advanced nodes (5 nm, 3 nm and below), using Synopsys and/or Cadence tool flows, preferably, targeting TSMC technologies. Own PPA and signoff closure for multi-million instance designs and drive successful production tape-outs while leading and mentoring a local PD team. Key Responsibilities Own complete physical design flow (floor planning, power planning, placement, CTS, routing,...

Job Title: Static Timing Analysis (STA) Engineer Job Overview We are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical expertise, problem-solving skills, and cross-functional collaboration. Key Responsibilities Perform Static Timing Analysis (setup, hold, recovery, removal) across all PVT corners and modes. Create, refine, and validate SDC constraints including clocks, generated clocks, false paths, and multi-cycle paths. Drive timing closure during synth...

We are looking for Test & Validation, Senior Manager to join the product validation team for PrimeTime. This is an exciting opportunity to lead a team of product validation engineers driving quality, working closely with R&D and product engineering to solve complex technical challenges in areas of static timing analysis. Job Responsibilities Mentor a team of engineers, set goals for the team and drive results Drive and execute quality improvement efforts Synopsys's PrimeTime tool by understanding requirements specifications and functional specifications, customer use cases Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement and execute comprehensive...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most?innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they?provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are?the same. Job Description Key Responsibilities: Timing Analysis & Closure Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations...

Alternate Job Titles: Senior Manager Product Validation Test & Validation Lead Manager Quality Assurance (PrimeTime) Validation Engineering Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished leader passionate about driving product quality and excellence. With a deep understanding of static timing an...

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are looking for a passionate & experienced EDA Methodology Engineer to join our timing team focusing on timing methodology using IBM Einstimer, Cadence & Synopsys...

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most?innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they?provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are?the same. Job Description Key Responsibilities: Timing Analysis & Closure Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations...

We are seeking a skilled and enthusiastic Digital Physical Design Engineer (G2) to contribute to the physical implementation of complex digital integrated circuits. This role involves working on various stages of the physical design flow, from synthesis to tape-out, ensuring performance, power, and area targets are met. Job Responsibilities * Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). * Perform physical verification (DRC, LVS, Antenna) and resolve related issues. * Conduct power integrity analysis (IR drop, EM) and optimize designs for power efficiency. * Participate in design-for-test (...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

Role Overview: As an STA Engineer, your primary responsibility will be timing closure and verification of complex ASIC or SoC designs. You will collaborate closely with cross-functional teams, including physical design, logic design, and architecture, to ensure timing requirements are met across various design stages and process corners. Key Responsibilities: - Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages - Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs - Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus) - Collaborate with design and architecture teams to defin...

At Capgemini Engineering, the world leader in engineering services, you will be part of a global team of engineers, scientists, and architects dedicated to helping innovative companies unleash their potential. Your role will involve providing unique R&D and engineering services across various industries, contributing to cutting-edge projects such as autonomous cars and life-saving robots. Join us for a career full of opportunities where you can make a difference every day. Key Responsibilities: - Timing Analysis & Closure - Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. - Achieve timing closure by resolving violations and optimizing paths. - Constraint De...

Job Details Job Description: As an IP Structural/Physical Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Overs...

Job Title: Physical Design Engineer Experience: 4+ Years Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Own block-level or full-chip implementation from RTL to GDSII. Perform: Floorplanning and placement Clock tree synthesis (CTS) Routing and optimization Run and close timing (STA), IR drop, EM, DRC, LVS, and a...

You are a Test & Validation, Staff Engineer responsible for joining the design intent testing team for STA & ECO at our company. In this role, you will have the exciting opportunity to work on product validation, qualifying tools with customer flows while collaborating closely with R&D and customers to address complex technical challenges in static timing analysis. By introducing innovative techniques and ideas, you will play a key role in enabling customers to accurately validate and implement these technologies in their high-performance designs. The ideal candidate for this position should be a self-motivated individual with a strong background in Static Timing Analysis & ECO. Additionally...

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally...

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies...

Experience : 5+years Location : Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners. Key Responsibilities: Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages. Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs. Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus). Collaborate with design and archi...

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally...

As an engineer at Synopsys, you will be a key player in driving innovations that shape the future of technology. Your role will involve working with cutting-edge tools and technologies to ensure the high quality and reliability of Synopsys's PrimeTime tool. You will collaborate with cross-functional teams to tackle complex technical challenges and provide valuable insights that influence the development and validation of future product releases. Your primary responsibilities will include executing and leading product validation of the PrimeTime tool, understanding requirements and functional specifications, and performing in-depth root cause analysis to enhance product quality. You will use ...

NVIDIA is continuously reinventing itself, with a rich history that includes inventing the GPU, which sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. The current global boom in artificial intelligence research demands highly scalable and massively parallel computation horsepower, a challenge where NVIDIA GPUs excel. As a part of NVIDIA, you will be joining a dynamic team focused on tackling difficult global challenges and amplifying human creativity and intelligence. The diverse and supportive environment at NVIDIA encourages everyone to strive for excellence and make a lasting impact on the world. NVIDIA is seeking a tal...

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurtur...