8 Synopsys Primetime Jobs

You are a Test & Validation, Staff Engineer responsible for joining the design intent testing team for STA & ECO at our company. In this role, you will have the exciting opportunity to work on product validation, qualifying tools with customer flows while collaborating closely with R&D and customers to address complex technical challenges in static timing analysis. By introducing innovative techniques and ideas, you will play a key role in enabling customers to accurately validate and implement these technologies in their high-performance designs. The ideal candidate for this position should be a self-motivated individual with a strong background in Static Timing Analysis & ECO. Additionally, knowledge of Power Analysis Flow, Parasitic Extraction Flow, Noise Delay, and Glitch Analysis Flow would be advantageous. Experience with Synopsys PrimeTime, ECO, and physical design closure will be considered a bonus. Proficiency in software and scripting skills such as Perl, Tcl, and Python is required, along with exceptional debugging skills. Previous exposure to Flow Test & Validation is also a desirable attribute. As a Test & Validation, Staff Engineer, your responsibilities will include driving quality improvement efforts by understanding customer design methodologies and flows. You will be tasked with creating in-house designs that replicate customer flows and use cases, as well as conducting thorough root cause analysis on customer incoming issues to identify weak areas and hot spots. By collaborating with cross-functional teams including R&D, Product Engineering, Field, and Customers, you will make recommendations for implementation and validation improvements. Your role will involve utilizing your product expertise to offer technical recommendations, diagnose and troubleshoot issues, and propose solutions to ensure product quality and readiness for customer deployment. Attention to detail and accuracy in all tasks are essential to demonstrate your commitment to excellence. If you are interested in exploring this opportunity, please share your updated CV with taufiq@synopsys.com. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without discrimination based on race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.,

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. Work with IP & Design team for Timing constraints Development & Review activities. Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance. Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the teams workflow. Prepare and present detailed timing reports and technical documentation to stakeholders Foster a culture of innovation, collaboration, and continuous improvement within the STA team. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. A minimum of 5 years of experience in Static Timing Analysis. Proven track record of successfully executing STA In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies. Strong understanding of digital design principles, physical design, and semiconductor fabrication processes. Excellent problem-solving skills and the ability to think strategically and analytically. Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders. Ability to prioritize tasks and manage multiple project work simultaneously. A proactive, results-oriented mindset with a passion for innovation and continuous improvement. Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying Show more Show less

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies. The ideal candidate should have 5-10 years of hands-on experience in Static Timing Analysis, a proven track record in full-chip STA and timing sign-off, a strong understanding of timing constraints, multi-mode/multi-corner (MMMC) flows, familiarity with scripting languages (TCL, Perl) and STA tools (preferably Synopsys PrimeTime), and excellent analytical, debugging, and cross-team communication skills. This position is based in Pune/Bangalore and requires an immediate notice period. Join ACL Digital to be a part of a dynamic team delivering next-gen semiconductor solutions. You will have the opportunity to work on cutting-edge technology projects with top-tier clients globally.,

Experience : 5+years Location : Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners. Key Responsibilities: Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages. Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs. Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus). Collaborate with design and architecture teams to define timing requirements and resolve timing violations. Analyze timing scenarios, margins, and corner cases. Integrate third-party IPs and derive timing signoff requirements. Optimize timing paths and reduce signoff corners by merging modes. Automate STA flows using scripting languages. Support test mode timing closure (e.g., scan shift, scan capture, BIST). Primary Skills: Static Timing Analysis (STA): Deep expertise in STA tools like Synopsys PrimeTime, Cadence Tempus. Timing Constraints Development: Proficient in writing and validating SDC constraints. Scripting Languages: Strong skills in TCL, Perl, Python for automation. ASIC/SoC Design Knowledge: Understanding of synthesis, physical design, and backend flows. Corner and Mode Analysis: Experience with timing corners, process variations, and signal integrity. Constraint Debugging: Familiarity with tools like Synopsys GCA (Galaxy Constraint Analyzer). Secondary Skills: Tool Proficiency: Experience with tools like Genus, Timevision, Fishtail, Tweaker. Low-Power Design: Knowledge of UPF, multi-voltage domains, and power gating. Custom IP Integration: Handling of PLLs, SerDes, ADC/DAC, GPIO, HSIO. Communication & Collaboration: Strong interpersonal skills for cross-functional teamwork. Mentorship: Ability to guide and mentor junior engineers. Process Node Experience: Familiarity with advanced nodes (3nm, 5nm, 7nm, FinFET). Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. Work with IP & Design team for Timing constraints Development & Review activities. Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance. Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the teams workflow. Prepare and present detailed timing reports and technical documentation to stakeholders Foster a culture of innovation, collaboration, and continuous improvement within the STA team. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. A minimum of 5 years of experience in Static Timing Analysis. Proven track record of successfully executing STA In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies. Strong understanding of digital design principles, physical design, and semiconductor fabrication processes. Excellent problem-solving skills and the ability to think strategically and analytically. Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders. Ability to prioritize tasks and manage multiple project work simultaneously. A proactive, results-oriented mindset with a passion for innovation and continuous improvement. Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying Show more Show less

As an engineer at Synopsys, you will be a key player in driving innovations that shape the future of technology. Your role will involve working with cutting-edge tools and technologies to ensure the high quality and reliability of Synopsys's PrimeTime tool. You will collaborate with cross-functional teams to tackle complex technical challenges and provide valuable insights that influence the development and validation of future product releases. Your primary responsibilities will include executing and leading product validation of the PrimeTime tool, understanding requirements and functional specifications, and performing in-depth root cause analysis to enhance product quality. You will use your expertise in Static Timing Analysis (STA) and tools like Synopsys PrimeTime to diagnose issues, propose innovative solutions, and ensure the readiness of the product for customer deployment. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python will enable you to streamline processes and improve efficiency. In this role, you will have a significant impact on enhancing customer satisfaction, driving continuous improvements in product design, and contributing to the overall success of Synopsys. You will play a crucial part in deploying cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. Your attention to detail, analytical thinking, and problem-solving mindset will be key to maintaining high standards of product quality and reliability. To excel in this role, you should have deep domain knowledge in Static Timing Analysis, a Bachelor's or Master's degree in Electrical Engineering or equivalent, and a minimum of 3-5 years of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, power, SDC constraints, and scripting skills are essential. As a collaborative team player with excellent communication skills, a proactive and self-motivated individual, and someone who thrives in a fast-paced environment, you will be a valuable addition to the product validation team for Synopsys's PrimeTime tool. Join us at Synopsys to transform the future through continuous technological innovation and be part of a team dedicated to ensuring the high quality of tools that drive the semiconductor industry forward.,

NVIDIA is continuously reinventing itself, with a rich history that includes inventing the GPU, which sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. The current global boom in artificial intelligence research demands highly scalable and massively parallel computation horsepower, a challenge where NVIDIA GPUs excel. As a part of NVIDIA, you will be joining a dynamic team focused on tackling difficult global challenges and amplifying human creativity and intelligence. The diverse and supportive environment at NVIDIA encourages everyone to strive for excellence and make a lasting impact on the world. NVIDIA is seeking a talented ASIC STA Engineer to join the Networking Silicon engineering team. In this role, you will contribute to the development of high-speed communication devices, ensuring the highest throughput and lowest latency for AI platforms. You will work on designing innovative large-scale chips and collaborate in a professional environment where your contributions matter. Key Responsibilities: - Lead full chip and/or chiplet level STA convergence from initial stages to signoff. - Contribute to top-level floor plan and clock planning. - Optimize CAD signoff flows and methodologies. - Integrate digital partitions and analog IPs timing, provide feedback to PD/RTL, and drive convergence. - Collaborate closely with logic design and DFT engineers to define and implement constraints for various work modes efficiently. Requirements: - B.Sc./M.Sc. in Electrical Engineering/Computer Engineering. - 3-8 years of experience in physical design and STA. - Proven expertise in RTL2GDS and STA design and convergence. - Familiarity with physical design EDA tools (e.g., Synopsys, Cadence). - Hands-on experience with STA using Synopsis Primetime. - Strong understanding of timing concepts and a collaborative team player. At NVIDIA, we have a team of forward-thinking individuals who are passionate about pushing boundaries. If you are a creative engineer who enjoys challenges and is ready to grow professionally, come be a part of our industry-leading physical design team. JR1995153,

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurturing their technical growth and promoting knowledge sharing within subsystem teams. Collaboration with various cross-functional teams will be essential to resolve design, timing, and physical implementation challenges that are specific to the integration of complex subsystems. Your qualifications should include a minimum of 10 years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, with expertise in advanced technology nodes such as 7nm or below. Proficiency in STA tools like Synopsys PrimeTime, Cadence Tempus, and PNR tools such as Synopsys ICC2, Cadence Innovus for application in large, multi-block, or hierarchical subsystems is required. A proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be skilled in scripting languages like Tcl, Perl, Python for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience in collaborating across frontend, physical design, and verification teams to integrate complex subsystems are crucial. Previous experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level would be advantageous. A background in high-speed interfaces or mixed-signal SoC subsystems is preferred for this role.,