6 Cadence Tempus Jobs

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. Work with IP & Design team for Timing constraints Development & Review activities. Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance. Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the teams workflow. Prepare and present detailed timing reports and technical documentation to stakeholders Foster a culture of innovation, collaboration, and continuous improvement within the STA team. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. A minimum of 5 years of experience in Static Timing Analysis. Proven track record of successfully executing STA In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies. Strong understanding of digital design principles, physical design, and semiconductor fabrication processes. Excellent problem-solving skills and the ability to think strategically and analytically. Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders. Ability to prioritize tasks and manage multiple project work simultaneously. A proactive, results-oriented mindset with a passion for innovation and continuous improvement. Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying Show more Show less

Experience : 5+years Location : Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners. Key Responsibilities: Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages. Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs. Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus). Collaborate with design and architecture teams to define timing requirements and resolve timing violations. Analyze timing scenarios, margins, and corner cases. Integrate third-party IPs and derive timing signoff requirements. Optimize timing paths and reduce signoff corners by merging modes. Automate STA flows using scripting languages. Support test mode timing closure (e.g., scan shift, scan capture, BIST). Primary Skills: Static Timing Analysis (STA): Deep expertise in STA tools like Synopsys PrimeTime, Cadence Tempus. Timing Constraints Development: Proficient in writing and validating SDC constraints. Scripting Languages: Strong skills in TCL, Perl, Python for automation. ASIC/SoC Design Knowledge: Understanding of synthesis, physical design, and backend flows. Corner and Mode Analysis: Experience with timing corners, process variations, and signal integrity. Constraint Debugging: Familiarity with tools like Synopsys GCA (Galaxy Constraint Analyzer). Secondary Skills: Tool Proficiency: Experience with tools like Genus, Timevision, Fishtail, Tweaker. Low-Power Design: Knowledge of UPF, multi-voltage domains, and power gating. Custom IP Integration: Handling of PLLs, SerDes, ADC/DAC, GPIO, HSIO. Communication & Collaboration: Strong interpersonal skills for cross-functional teamwork. Mentorship: Ability to guide and mentor junior engineers. Process Node Experience: Familiarity with advanced nodes (3nm, 5nm, 7nm, FinFET). Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. Work with IP & Design team for Timing constraints Development & Review activities. Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance. Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the teams workflow. Prepare and present detailed timing reports and technical documentation to stakeholders Foster a culture of innovation, collaboration, and continuous improvement within the STA team. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. A minimum of 5 years of experience in Static Timing Analysis. Proven track record of successfully executing STA In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies. Strong understanding of digital design principles, physical design, and semiconductor fabrication processes. Excellent problem-solving skills and the ability to think strategically and analytically. Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders. Ability to prioritize tasks and manage multiple project work simultaneously. A proactive, results-oriented mindset with a passion for innovation and continuous improvement. Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying Show more Show less

Static Timing Analysis (STA) Engineer with hands-on experience in timing validation, analysis, and closure for complex SoC designs. Should have a strong background in STA flows using Tempus, along with a solid understanding of deep submicron nodes. Required Candidate profile Expertise in STA using Cadence Tempus, timing validation across multiple PVT corners, DMMMC flows, and timing closure at both block and full-chip levels, skills in TCL and Python are essential

5+y in STA,tcl, python scripting Timing analysis,validation,debug Tempus DMMMC flow for STA STA setup,convergence, reviews,signoff for scan,function Endpoints,check timing reports,timing methodologies,noise, crosstalk,OCV Lower nodes 22nm,16nm,5nm

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurturing their technical growth and promoting knowledge sharing within subsystem teams. Collaboration with various cross-functional teams will be essential to resolve design, timing, and physical implementation challenges that are specific to the integration of complex subsystems. Your qualifications should include a minimum of 10 years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, with expertise in advanced technology nodes such as 7nm or below. Proficiency in STA tools like Synopsys PrimeTime, Cadence Tempus, and PNR tools such as Synopsys ICC2, Cadence Innovus for application in large, multi-block, or hierarchical subsystems is required. A proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be skilled in scripting languages like Tcl, Perl, Python for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience in collaborating across frontend, physical design, and verification teams to integrate complex subsystems are crucial. Previous experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level would be advantageous. A background in high-speed interfaces or mixed-signal SoC subsystems is preferred for this role.,