Static Timing Analysis (STA) Engineer

5 - 10 years

15 - 25 Lacs

Posted:16 hours ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

Static Timing Analysis (STA) Engineer with hands-on experience in timing validation, analysis, and closure for complex SoC designs. Should have a strong background in STA flows using Tempus, along with a solid understanding of deep submicron nodes.

Required Candidate profile

Expertise in STA using Cadence Tempus, timing validation across multiple PVT corners, DMMMC flows, and timing closure at both block and full-chip levels, skills in TCL and Python are essential

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