Senior Engineer, Physical Design

Your Team, Your Impact

What You Can Expect

You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Every day, you ll be working hands-on to triage workflows, whether you re running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc. There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it s your responsibility to review completed runs for errors or create optimizations from successful runs.

What Were Looking For

• Bachelor s, Master s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.

• 3+ years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e. g. , 7nm, 5nm, or below).
• Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler and Fusion Compiler.
• Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous.
• Working knowledge of physical verification and formal verification tools (e. g. , Calibre, LEC, Formality) is advantageous.
• Enjoy learning by doing the work and having access to guides and a mentor.
• Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before.