4 Crosstalk Jobs

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues. Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have leadership qualities and able to do multi-tasking as required. Should be able to work in a team environment and able to guide and provide technical support to the fellow team members. Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus. mandatory skillset: stdcells layout || cadence virtuoso || physical verifications checks

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues. Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have leadership qualities and able to do multi-tasking as required. Should be able to work in a team environment and able to guide and provide technical support to the fellow team members. Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus. mandatory skillset: stdcells layout || cadence virtuoso || physical verifications checks

Static Timing Analysis (STA) Engineer with hands-on experience in timing validation, analysis, and closure for complex SoC designs. Should have a strong background in STA flows using Tempus, along with a solid understanding of deep submicron nodes. Required Candidate profile Expertise in STA using Cadence Tempus, timing validation across multiple PVT corners, DMMMC flows, and timing closure at both block and full-chip levels, skills in TCL and Python are essential

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a global leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Joining our inclusive team means focusing on relentless innovation for customers and partners, contributing to integrity, sustainability, and community support to drive the very innovation we pursue. As a CAD Applications Engineer at Micron Technology, Inc., you will collaborate in a production support role to evaluate and enhance Electronic Design Automation (EDA) tools and flows for STA Analysis. Your role involves working closely with Design teams to enhance their productivity and efficiency. Responsibilities and Tasks: - Deliver methodology and tool solutions for static timing closure and power optimization. - Deploy innovative modeling and optimization approaches to achieve globally optimal targets. - Apply best-in-class algorithms and ECO techniques for value-adding design solutions. - Conduct deep analysis of timing paths and power inefficiencies to isolate key issues. - Implement code infrastructure to enable analytics and visualization. - Collaborate with silicon design, CAD, and EDA partners to identify flow deficiencies and implement creative remedies. Qualifications: - Requires 10+ years of hands-on experience in static timing analysis and/or design optimization flows. - Familiarity with STA of large high-performance Memory technologies. - Strong analytical skills to identify high ROI opportunities. - Software engineering background with experience in C++, Python, Tcl programming languages. - Understanding of cross-talk, variation, and margining. - Effective communicator to assess and describe issues accurately to management. - Familiarity with timing and power ECO techniques and implementation is a plus. - Knowledge of TSMC based designs will be an added advantage. - Leading IP delivery project experience is also beneficial. About Micron Technology, Inc.: Micron is a pioneer in memory and storage solutions, transforming how information is used to enrich lives globally. With a customer-centric approach, technology leadership, and operational excellence, Micron delivers high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. Our innovations power the data economy, enabling advancements in artificial intelligence and 5G applications across various platforms. For more information, visit micron.com/careers. For assistance with the application process or reasonable accommodations, contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and complies with all relevant laws, rules, regulations, and international labor standards.,