17 Constraint Development Jobs

At Capgemini Engineering, the world leader in engineering services, you will be part of a global team of engineers, scientists, and architects dedicated to helping innovative companies unleash their potential. Your role will involve providing unique R&D and engineering services across various industries, contributing to cutting-edge projects such as autonomous cars and life-saving robots. Join us for a career full of opportunities where you can make a difference every day. Key Responsibilities: - Timing Analysis & Closure - Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. - Achieve timing closure by resolving violations and optimizing paths. - Constraint De...

As an ASIC/SoC Design Engineer at Qualcomm India Private Limited, you will be responsible for Logic design, micro-architecture, RTL coding, and integration for complex SoCs. Your expertise in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, and APB will be crucial. You will collaborate with verification and validation teams, work on low power SoC design, multi-clock designs, and asynchronous interfaces. Your experience with tools like Lint, CDC, Design compiler, and Primetime will be essential for successful ASIC development. Additionally, your understanding of constraint development, timing closure, and synthesis concepts will be beneficial. **Key Responsibilities:**...

As a Senior SoC Design Engineer at Qualcomm India Private Limited, you will be utilizing your 10-16 years of experience in SoC design. Your responsibilities will include working with AMBA protocols such as AXI, AHB, and APB, understanding SoC clocking/reset/debug architecture, and dealing with peripherals like USB, PCIE, and SDCC. It is crucial to have expertise in memory controller designs, microprocessors, constraint development, and timing closure. Collaboration with SoC verification and validation teams for pre/post Silicon debug will be an integral part of your role. Additionally, hands-on experience in Low power SoC design, Multi Clock designs, Asynchronous interface, and proficiency i...

As an experienced Logic Design Engineer at Qualcomm India Private Limited, your role will involve the following key responsibilities: - Hands-on experience in Logic design, micro-architecture, and RTL coding, with a strong emphasis on SoC design and integration for complex SoCs. - Proficiency in Verilog and System-Verilog, along with a solid understanding of AMBA protocols like AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. - Knowledge of Memory controller designs, microprocessors, and experience in constraint development and timing closure. - Collaboration with the SoC verification and validation teams for pre/post Silicon...

Role Overview: As a Hardware Engineer at Qualcomm, you will be responsible for the Logic design, micro-architecture, and RTL coding of complex SoCs. Your expertise will be crucial in ensuring the successful design and integration of SoCs, as well as collaborating with verification and validation teams for pre/post Silicon debug. Key Responsibilities: - Hands-on experience with SoC design and integration - Proficiency in Verilog/System-Verilog - Knowledge of AMBA protocols such as AXI, AHB, and APB - Understanding of SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC - Familiarity with Memory controller designs and microprocessors - Experience in constraint deve...

You have a rewarding opportunity at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering team. As a Senior SoC Design Engineer, you will play a crucial role with your extensive experience in SoC design and expertise in various protocols and architectures. Let's delve deeper into the responsibilities and qualifications required for this role: **Role Overview:** - Utilize your 15+ years of experience in SoC design to contribute effectively to the team - Demonstrate proficiency in AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture - Showcase your knowledge of peripherals like USB, PCIE, and SDCC - Gain an under...

As a Staff Digital Design Engineer at our company, you will play a crucial role in leading the micro-architecture and implementation of advanced digital subsystems for automotive Ethernet communication systems. You will collaborate with both analog and digital teams to deliver high-performance and reliable solutions for next-generation automotive networks. **Key Responsibilities:** - Design and verify digital blocks for Ethernet MAC, PCS, and Base-T PHY layers - Micro-architect and implement Digital Front-End (DFE) designs for automotive PHYs - Integrate analog IPs and collaborate with analog and communication systems teams - Lead subsystem creation including clocking, reset, and power manag...

You should have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include designing and developing CXL and DRAM controller (DDR4/5) based intellectual property, engaging with other architects within the IP level to drive the Micro-Architectural definition, delivering quality micro-architectural level documentation, producing quality RTL on schedule by meeting PPA goals, being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. You will collaborate with the verification team to ensure implementation meets architectural intent, run quality checks such as Lint, CDC, and ...

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Mult...

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in usi...

This role is for an STA Engineer to be a key contributor in the synthesis and static timing analysis of complex SoCs. The ideal candidate will have extensive experience in timing closure, I/O constraint development for industry-standard protocols, and hands-on experience with advanced technology nodes. Responsibilities Perform synthesis of complex SoCs at both block and top levels. Develop and write timing constraints for intricate designs, including those with multiple clocks and voltage domains. Lead post-layout timing closure for multiple tape-outs, including handling timing ECOs and achieving STA signoff. Develop I/O constraints for industry-standard protocols such as DDR1/2/3, SDR, LPDD...

We are seeking a highly skilled Low Power Formal Verification Engineer to join our team. The ideal candidate will possess deep expertise in low power formal verification, advanced constraint development, and a strong understanding of timing analysis in complex SoC designs. This role is critical for ensuring the power efficiency and functional correctness of our designs through rigorous verification methodologies. Roles and Responsibilities: Utilize work experience in Advanced Constraint Verification & post-layout STA (Static Timing Analysis) . Apply expertise in Low Power Formal Verification techniques to ensure power efficiency and functional correctness. Demonstrate expertise in Constraint...

Qualcomm India Private Limited is looking for a Hardware Engineer with over 12 years of experience in SoC design. You should have a strong understanding of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. Knowledge of memory controller designs and microprocessors would be an added advantage. In this role, you will be responsible for constraint development and timing closure, working closely with SoC verification and validation teams for pre/post Silicon debug. Hands-on experience in Low power SoC design is required, along with expertise in Synthesis and understanding of timing concepts for ASIC. You should...

You should be well versed with timing closure (STA) and timing closure methodologies, along with the ability to develop pre/post-layout constraints for timing closure. You will be required to collaborate with the design team to establish functional/DFT constraints and integrate IP level constraints. Additionally, you should have experience in defining multi-voltage/switching aware corner definitions, selecting RC/C models, and possessing expertise in abstraction techniques such as Hyperscale/ILM/ETM. In this role, you will be responsible for conducting RC balancing and scaling analysis of full chip clocks as well as critical data paths. Proficiency in automation using PERL, TCL, and EDA tool...

You should have knowledge of AMBA protocols including AXI, AHB, APB, SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. An understanding of memory controller designs and microprocessors would be an added advantage. Hands-on experience in constraint development and timing closure is essential for this role. You will be required to work closely with the SoC verification and validation teams for pre and post Silicon debug. Experience in Low power SoC design is a must-have for this position. You should also have experience in Synthesis and a good understanding of timing concepts for ASIC. Hands-on experience in Multi Clock designs and Asynchronous interface is a k...

Qualcomm India Private Limited is seeking a Software Engineer with expertise in various aspects of System on Chip (SoC) architecture and design. In this role, you will be responsible for working with AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. An understanding of Memory controller designs and microprocessors is considered an added advantage for this position. As a Software Engineer at Qualcomm, you will be required to have hands-on experience in constraint development and timing closure. Additionally, you will collaborate closely with the SoC verification and validation teams for pre/post Silicon debu...

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on ...