Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Logic Design Engineer to join our MIC IDC Design team in Bengaluru In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer, As a PE Logic Design Engineer, youll play a pivotal role in designing and implementing the worlds best Registered Clocking Driver (RCD) products In this full-time role, youll report directly to our Logic Design Manager Our MIC IDC is dedicated to leverage over three decades of high-performance memory expertise to deliver cutting-edge memory interface chipset solutions, enhancing memory bandwidth and capacity for data centers and client applications alike, and your contributions will be instrumental in RCD product development, Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work Responsibilities Understand the spec requirements and convert into a micro architecture specification, Realize the RTL design using Verilog/System Verilog, Works with verification teams in defining the test plan and reviews the test coverage, Does pre implementation design checks like lint, CDC, RDC, constraint validation, Works with physical design team in defining the design and timing constraints and driving implementation till timing closure, Interact with cross functional circuit teams for new product development Participate in Architecture level discussions to define the specifications, Post silicon validation support in bringing up parts, Qualifications Minimum 10 years of solid ASIC logic/Digital design expertise with bachelors degree or masters degree Strong digital design fundamentals, Strong hands on expertise in HDLs like Verilog/System Verilog, Experience with EDA tools for simulation, synthesis, and timing analysis and logic equivalence check, Knowledge of High speed protocols is plus, Strong scripting abilities using Perl/Tcl/python is a plus Strong written and verbal communication skills Able to break down technical concepts to a larger audience is desired, About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems, Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits, Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard, Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics, Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures If you require assistance or an accommodation due to a disability, please feel free to inform us in your application, Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services, For more information about Rambus, visit rambus For additional information on life at Rambus and our current openings, check out rambus /careers/,

Overview: Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities: Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip’s for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications: Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

Overview: Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities: Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip’s for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications: Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

Overview We are seeking a highly skilled and motivated Post-Silicon Validation Engineer to join our dynamic team. As a Post-Silicon Validation Engineer your primary focus will be on developing and executing comprehensive validation plans, debugging complex issues, and collaborating closely with cross-functional teams to drive product quality and success. Responsibilities Collaborate with design and verification teams to define validation plan, strategies, objectives, and requirements for post-silicon validation activities. Develop and implement validation tests, including test benches, test cases, and automation scripts, to validate the functionality and performance of the silicon. Execute validation tests on silicon prototypes and evaluate results to identify and diagnose design defects, functional issues, and performance bottlenecks. Analyze and debug complex issues to identify root causes and work closely with design, architecture, and software teams to propose and implement effective solutions. Continuously improve and maintain the validation infrastructure, including test automation frameworks, tools, and methodologies, to streamline validation processes and increase productivity. Collaborate with cross-functional teams, including design, verification, software, and system teams, to drive product quality, resolve issues, and ensure timely product releases. Prepare comprehensive validation reports, including test plans, test procedures, and defect tracking documentation, to communicate validation progress, results, and recommendations. Stay up-to-date with the latest industry trends, emerging technologies, and best practices in post-silicon validation to enhance your technical expertise and contribute to process improvements. Qualifications Bachelor's or Master’s degree in Electrical Engineering, Electronics or a related field. Advanced degree is a plus. 5-8 years of experience in high-speed IO validation and debugging, with preferable knowledge in DDR protocol validation. Solid understanding of semiconductor device architectures, digital logic design, and verification methodologies. Proficiency in programming languages such as C/C++, Python, or scripting languages used in test automation. Hands-on experience with validation tools and methodologies, such as simulation tools, logic analyzers, oscilloscopes, BERT scope and JTAG debuggers. Strong analytical and problem-solving skills with the ability to debug complex hardware and software interactions. Excellent communication and interpersonal skills to collaborate effectively with cross-functional teams. Ability to work independently and multitask in a fast-paced environment with a high attention to detail.

Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe and CXL Controller Soft IP development and PHYs integrations, on leading-edge PCI-Express and CXL controller technologies This is a Full Time position Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles Responsibilities Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module Verifying the IP integration with dedicated simulation environment Development and support test cases of different verification environments Support worldwide customers on the IP integration Get familiar to existing verification process, propose improvements Maintain the traceability from the customer specification or the product specification to the architecture and verification results Track and maintain verification productivity metrics Reporting periodically on progress and difficulties Qualifications Positive and self-driven achiever with: "Can Do" Attitude Bachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplines Strong analytical and problem-solving skills Excellent interpersonal skills Open for traveling abroad Work in international organization and specially with teams in France, USA, Taiwan and India Because Rambus operates internationally, very good English is important for the position Your technical experience: 6+ years experience verification with Verilog, SystemVerilog, FPGA prototyping 6+ years experience with complex ASIC/VLSI verification 6+ years experience with Avery or UVM Any 3rd party VIP experience is a plus 6+ years experience in multinational company Experience with creating documentation, python, shell & etc About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures If you require assistance or an accommodation due to a disability, please feel free to inform us in your application Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services For more information about Rambus, visit rambus, For additional information on life at Rambus and our current openings, check out rambus,/careers/

Overview We are seeking a highly skilled and motivated Post-Silicon Validation Engineer to join our dynamic team. As a Post-Silicon Validation Engineer your primary focus will be on developing and executing comprehensive validation plans, debugging complex issues, and collaborating closely with cross-functional teams to drive product quality and success. Responsibilities Collaborate with design and verification teams to define validation plan, strategies, objectives, and requirements for post-silicon validation activities. Develop and implement validation tests, including test benches, test cases, and automation scripts, to validate the functionality and performance of the silicon. Execute validation tests on silicon prototypes and evaluate results to identify and diagnose design defects, functional issues, and performance bottlenecks. Analyze and debug complex issues to identify root causes and work closely with design, architecture, and software teams to propose and implement effective solutions. Continuously improve and maintain the validation infrastructure, including test automation frameworks, tools, and methodologies, to streamline validation processes and increase productivity. Collaborate with cross-functional teams, including design, verification, software, and system teams, to drive product quality, resolve issues, and ensure timely product releases. Prepare comprehensive validation reports, including test plans, test procedures, and defect tracking documentation, to communicate validation progress, results, and recommendations. Stay up-to-date with the latest industry trends, emerging technologies, and best practices in post-silicon validation to enhance your technical expertise and contribute to process improvements. Qualifications Bachelor's or Master’s degree in Electrical Engineering, Electronics or a related field. Advanced degree is a plus. 5-8 years of experience in high-speed IO validation and debugging, with preferable knowledge in DDR protocol validation. Solid understanding of semiconductor device architectures, digital logic design, and verification methodologies. Proficiency in programming languages such as C/C++, Python, or scripting languages used in test automation. Hands-on experience with validation tools and methodologies, such as simulation tools, logic analyzers, oscilloscopes, BERT scope and JTAG debuggers. Strong analytical and problem-solving skills with the ability to debug complex hardware and software interactions. Excellent communication and interpersonal skills to collaborate effectively with cross-functional teams. Ability to work independently and multitask in a fast-paced environment with a high attention to detail.