Position: STA Lead Engineer Cluster Level Location: Bangalore, India Experience: 8–12 years in Static Timing Analysis (STA) About the Role We are seeking a Static Timing Analysis (STA) Lead to drive cluster-level timing closure for advanced SoCs. The role involves owning STA strategy, guiding a team of 7–8 engineers, and collaborating across RTL, Physical Design, and Sign-off teams to ensure robust, production-ready silicon. Key Responsibilities Lead and mentor a team of STA engineers, providing technical direction, task allocation, and performance feedback. Own cluster-level STA sign-off , including setup/hold, clock skew, jitter, crosstalk, and OCV analysis. Develop and validate SDC constraints and timing methodologies for multiple functional and test modes Collaborate closely with Physical Design, RTL, and DFT teams to achieve timing closure. Drive ECO implementation for timing fixes without impacting functionality. Interface with EDA vendors to resolve tool and flow issues. Ensure delivery schedules are met with high-quality, sign-off-ready timing reports. Contribute to timing methodology improvements and automation for enhanced productivity. Required Skills & Experience 7+ years of hands-on STA experience Strong command over PrimeTime or Cadence Tempus and SDC constraint development. Deep understanding of multi-mode, multi-corner (MMMC) analysis . Proven experience in ECO flow and debugging complex timing paths. Strong leadership, mentoring, and cross-functional coordination skills. Preferred Qualifications Exposure to high-performance computing, AI, or networking SoCs . Familiarity with power-aware STA and UPF/CPF flows. Experience in developing STA automation scripts (Tcl/Perl/Python). Why Join Us? Work on cutting-edge, high-performance SoCs in a collaborative environment where technical leadership and innovation are valued. Be a key contributor to silicon success in next-gen computing architectures.
Location: Bangalore Experience: 8+ Years | Type: Full-Time Domain: Semiconductor / ASIC Design & Verification / Wireless IP Industry: VLSI / Semiconductor Services About the Role Were seeking a highly skilled Design Verification (DV) Engineer to take ownership of verifying Bluetooth IPs and subsystems for advanced wireless SoCs. Youll architect and execute UVM-based verification environments, drive feature closure for PHY/MAC layers, and ensure full compliance with Bluetooth BR/EDR, BLE, BT 5.x/5.4 and IEEE 802.15.1 standards. This is a high-impact, hands-on role where your expertise will directly influence next-generation automotive, IoT, and processor solutions. Key Responsibilities Architect, develop, and maintain SystemVerilog UVM testbenches for Bluetooth controller IP/subsystems (PHY/MAC/LL) . Define and execute comprehensive verification plans covering Bluetooth protocol layers and custom enhancements. Verify key Bluetooth hardware blocks: Link Layer (LL) Baseband Controller (BBC) Adaptive Frequency Hopping (AFH) LE Advertising & Scanning HCI (Host Controller Interface) AES-CCM encryption/decryption Bluetooth Low Energy PHY (1M, 2M, Coded PHY) Develop assertions, checkers, and scoreboards for protocol compliance and functional correctness. Drive debug using Verdi, DVE, VCS, Questa, performing root cause analysis for RTL and TB issues. Collaborate with architects, RTL, firmware, and validation teams to ensure spec alignment and issue resolution. Ensure functional and code coverage closure; maintain regression dashboards and quality metrics. Lead formal reviews and sign-off for verification deliverables, test cases, and documentation. Required Technical Skills Expert-level SystemVerilog UVM skills; proven ability to build scalable, modular environments. Strong debugging and waveform analysis experience (Verdi/DVE/VCS/Questa). In-depth knowledge of Bluetooth 5.0/5.2/5.4 specifications – Link Layer, LE PHYs, HCI. Solid understanding of IEEE 802.15.1, Bluetooth SIG compliance, and LMP procedures. Why Join Us?Work on cutting-edge wireless technologies powering the future of automotive, IoT, and high-performance processors. Full lifecycle exposure – from spec to tape-out. Collaborate with world-class semiconductor experts in an innovation-driven culture. Competitive compensation and strong career growth path
We're Hiring: Design Verification Trained Freshers (M.Tech/M.E) | AI Product Team | Siplont Technologies Are you a Masters graduate (M.Tech/M.E) with training in Design Verification and a passion to work on cutting-edge AI-driven semiconductor products ? Join Siplont Technologies , where were building the future of intelligent chip design! What We're Looking For Freshers trained in Design Verification (SV/UVM) Strong understanding of Digital Design, Verilog, SystemVerilog, UVM Passion for AI-based hardware development Excellent problem-solving and debugging skills Commitment to long-term career growth with us Why You Should Join Us Be part of a next-gen AI-focused product team Learn directly under an industry stalwart with 30+ years of experience in Design Verification Our technical leader has: Worked with top semiconductor giants Led 20+ successful chip tape-outs Spearheaded multiple global verification teams Build your career where innovation meets mentorship Key Skills You'll Work On SystemVerilog , UVM , Verilog RTL Verification , Testbench Architecture Assertions , Functional Coverage Exposure to AI, ML-integrated chip design Debug using Simulators (VCS/Questa) and Waveform tools At Siplont, we don’t just offer jobs — we offer career journeys . If you’re passionate about silicon and serious about staying long-term to grow into a core contributor to AI-enabled chip design , this is your chance . Preferred candidate profile