Lead Design Verification Engineer(Bluetooth IP Sub-System)

Location: Bangalore

Experience: 8+ Years | Type: Full-Time

Domain: Semiconductor / ASIC Design & Verification / Wireless IP

Industry: VLSI / Semiconductor Services

About the Role

Were seeking a highly skilled Design Verification (DV) Engineer to take ownership of verifying Bluetooth IPs and subsystems for advanced wireless SoCs. Youll architect and execute UVM-based verification environments, drive feature closure for PHY/MAC layers, and ensure full compliance with Bluetooth BR/EDR, BLE, BT 5.x/5.4 and IEEE 802.15.1 standards.

This is a high-impact, hands-on role where your expertise will directly influence next-generation automotive, IoT, and processor solutions.

Key Responsibilities

• Architect, develop, and maintain SystemVerilog UVM testbenches for

  Bluetooth controller IP/subsystems (PHY/MAC/LL)

  .
• Define and execute comprehensive verification plans covering Bluetooth protocol layers and custom enhancements.
• Verify key Bluetooth hardware blocks:
• Link Layer (LL)
• Baseband Controller (BBC)
• Adaptive Frequency Hopping (AFH)
• LE Advertising & Scanning
• HCI (Host Controller Interface)
• AES-CCM encryption/decryption
• Bluetooth Low Energy PHY (1M, 2M, Coded PHY)
• Develop assertions, checkers, and scoreboards for protocol compliance and functional correctness.
• Drive debug using Verdi, DVE, VCS, Questa, performing root cause analysis for RTL and TB issues.
• Collaborate with architects, RTL, firmware, and validation teams to ensure spec alignment and issue resolution.
• Ensure functional and code coverage closure; maintain regression dashboards and quality metrics.
• Lead formal reviews and sign-off for verification deliverables, test cases, and documentation.

Required Technical Skills

• Expert-level SystemVerilog UVM skills; proven ability to build scalable, modular environments.
• Strong debugging and waveform analysis experience (Verdi/DVE/VCS/Questa).
• In-depth knowledge of Bluetooth 5.0/5.2/5.4 specifications – Link Layer, LE PHYs, HCI.
• Solid understanding of IEEE 802.15.1, Bluetooth SIG compliance, and LMP procedures.
• Why Join Us?Work on cutting-edge wireless technologies powering the future of automotive, IoT, and high-performance processors.
• Full lifecycle exposure – from spec to tape-out.
• Collaborate with world-class semiconductor experts in an innovation-driven culture.
• Competitive compensation and strong career growth path