Design Verification Lead

Greetings!

Requirement

Senior / Lead SoC Verification Engineers

• Experience:

  6 to 20 years

• Location:

  Hyderabad

• Notice Period:

  Less than 30 days (mandatory)

Skill Set Summary

• Extensive hands-on experience in

  Subsystem and Full-Chip SoC Verification

• Expert-level proficiency in

  SystemVerilog, UVM

  , and advanced verification methodologies
• Strong experience defining

  verification strategies, test plans, and coverage models

  for complex SoCs
• Deep protocol expertise in

  AXI4 / AHB / APB

  , including performance, coherency, and corner-case scenarios
• Experience verifying

  Microcontroller / Microprocessor-based SoCs

• Strong background in

  verification IP development

  , customization, and reuse
• Hands-on experience with

  SVA, functional coverage, constrained-random testing

• Exposure to

  power-aware verification

  , reset sequencing, multi-clock and multi-reset domains
• Experience in

  SoC-level debug

  , silicon bring-up support, and pre/post-silicon correlation is a plus
• Ability to

  lead verification reviews

  , mentor junior engineers, and drive best practices
• Strong communication skills to interface with

  global stakeholders and customer-facing teams

Interested candidates can reach out directly at: