Design Verification Lead

As a Design Verification Lead at Edveon, you will play a crucial role in the VLSI team in Chennai. Your responsibilities will include: - Leading end-to-end verification for complex SoC/IP projects - Developing UVM-based testbenches and verification environments from scratch - Driving functional and code coverage closure - Ensuring high-quality, first-time-right silicon through thorough validation - Collaborating with design, architecture, and validation teams To excel in this role, you should possess the following qualifications: - 7 to 15 years of experience in Design Verification - Strong hands-on expertise in SystemVerilog and UVM - Good understanding and working knowledge of RAL (Register Abstraction Layer) - Experience with tools like VCS, Questa, or equivalent simulators - Solid understanding of coverage, assertions, and debugging techniques - Prior experience in leading verification teams or projects is a plus If you are seeking to lead impactful projects and contribute to a dynamic semiconductor team, we encourage you to apply by sending your CV, notice period, and current CTC details to recruitment@edveon.com.,