Senior Design Verification Engineer

Job Title: Design Verification Lead Location: Chennai (TN) / California, USA Mode: Hybrid Experience: 7 to 15 years Contact Email: recruitment@edveon.com CTC: Best in the industry Job Description: Edveon is hiring an experienced Design Verification Lead to join our growing VLSI team in Chennai. We are looking for a technically strong and hands-on professional with 7 to 15 years of experience in ASIC/FPGA Design Verification, specializing in SystemVerilog (SV) and UVM. Key Responsibilities: Lead end-to-end verification for complex SoC/IP projects Develop UVM-based testbenches and verification environments from scratch Drive functional and code coverage closure Ensure high-quality, first-time-right silicon through thorough validation Collaborate with design, architecture, and validation teams Required Skills: 7 to 15 years of experience in Design Verification Strong hands-on expertise in SystemVerilog and UVM Good understanding and working knowledge of RAL (Register Abstraction Layer) Experience with tools like VCS, Questa, or equivalent simulators Solid understanding of coverage, assertions, and debugging techniques Prior experience in leading verification teams or projects is a plus If you're looking to lead impactful projects and be part of a dynamic semiconductor team, apply now at recruitment@edveon.com with your CV, notice period and current CTC details. Show more Show less