9 Ral Jobs

1. 12-18 Yrs in DV full-chip Exp. 2. Experience in SV/UVM testbench verification 3. Experience in ARM Coresight Debug subsystem 4. CSI/ DSI protocol expertise 5. Memory controller or cache expertise 6. Hands-on RAL model development (UVM) Required Candidate profile • EXP in verifying successful IPs, Subsystems & or SoCs. • PC System Architecture: PCI Express, USB, Ethernet, HyperTransport, DDR. • Standard bus/interface protocols (i.e. AXI, AHB, AMBA, OCP, PIPE).

As a Design Verification Lead at Edveon, you will play a crucial role in the VLSI team in Chennai. Your responsibilities will include: - Leading end-to-end verification for complex SoC/IP projects - Developing UVM-based testbenches and verification environments from scratch - Driving functional and code coverage closure - Ensuring high-quality, first-time-right silicon through thorough validation - Collaborating with design, architecture, and validation teams To excel in this role, you should possess the following qualifications: - 7 to 15 years of experience in Design Verification - Strong hands-on expertise in SystemVerilog and UVM - Good understanding and working knowledge of RAL (Registe...

order General information #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness,...

order General information #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness,...

The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and deve...

1. 10-15 Yrs in DV full-chip Exp. 2. Experience in SV/UVM testbench verification 3. Experience in ARM Coresight Debug subsystem 4. CSI/ DSI protocol expertise 5. Memory controller or cache expertise 6. Hands-on RAL model development (UVM) Required Candidate profile • EXP in verifying successful IPs, Subsystems & or SoCs. • PC System Architecture: PCI Express, USB, Ethernet, HyperTransport, DDR. • Standard bus/interface protocols (i.e. AXI, AHB, AMBA, OCP, PIPE).

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer based in Siruseri, Chennai. In this role, you will have the opportunity to work closely with a top-tier client and play a pivotal role in developing next-gen chip-level verification environments utilizing System Verilog and UVM methodologies. This is a full-time position that requires you to work from the office. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. Your tasks will include developing verification test plans based on detailed design specifications, constructing UVM-based simulati...

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai! In this role, you will have the opportunity to work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. You will play a crucial role in developing verification test plans based on detailed design specifications and constructing UVM-based simulation environments using System Verilog. Additionally, you will...

Job Title: Senior / Lead Design Verification Engineer Experience: 6 10 years Location: Siruseri, Chennai (Work from Office only) Industry: Semiconductor / VLSI Employment Type: Full-time / Permanent Key Responsibilities: Perform functional verification at block and chip level for complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs or subsystems. Develop and execute detailed verification test plans based on design specifications. Write directed and constrained-random test cases; debug simulation failures. Perform coverage analysis (functional and code) and drive closure. Work with RAL (Register Abstraction Layer) to verify register-level functionality. Develop and v...