4 Ral Jobs

1. 10-15 Yrs in DV full-chip Exp. 2. Experience in SV/UVM testbench verification 3. Experience in ARM Coresight Debug subsystem 4. CSI/ DSI protocol expertise 5. Memory controller or cache expertise 6. Hands-on RAL model development (UVM) Required Candidate profile • EXP in verifying successful IPs, Subsystems & or SoCs. • PC System Architecture: PCI Express, USB, Ethernet, HyperTransport, DDR. • Standard bus/interface protocols (i.e. AXI, AHB, AMBA, OCP, PIPE).

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer based in Siruseri, Chennai. In this role, you will have the opportunity to work closely with a top-tier client and play a pivotal role in developing next-gen chip-level verification environments utilizing System Verilog and UVM methodologies. This is a full-time position that requires you to work from the office. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. Your tasks will include developing verification test plans based on detailed design specifications, constructing UVM-based simulation environments using System Verilog, analyzing coverage to ensure completeness, implementing assertion-based verification for functional robustness, validating register-level behaviors with RAL, collaborating across functions to synchronize design and verification milestones, and creating testbenches for simulation and performance efficiency. The ideal candidate for this role should have a minimum of 6 to 10 years of experience in design verification. You should be well-versed in System Verilog, UVM, and ASIC verification methodologies. If you are passionate about making a significant impact in chip-level verification and are ready to contribute to cutting-edge projects, we encourage you to apply for this position by sending your resume to Venkatesh@coventine.com or by contacting us directly. Join our team at Coventine Digital Private Limited and be part of a dynamic environment where your skills and expertise in design verification will be valued and recognized. Take the next step in your career and explore the exciting opportunities that await you in the field of chip design and verification. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai! In this role, you will have the opportunity to work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. You will play a crucial role in developing verification test plans based on detailed design specifications and constructing UVM-based simulation environments using System Verilog. Additionally, you will conduct coverage analysis to ensure the validation's completeness, implement assertion-based verification to guarantee functional robustness, and collaborate across teams to align design and verification milestones. Your tasks will also involve working with RAL to validate register-level behaviors, creating testbenches for simulation, and optimizing performance efficiency. If you have 6 to 10 years of relevant experience and are eager to make a significant impact in chip-level verification, we encourage you to apply for this permanent position. This is a Work from Office opportunity located in Siruseri, Chennai. Immediate joiners are preferred. Don't miss this chance to be part of a dynamic team and contribute to cutting-edge chip design projects. Send your resume to Venkatesh@coventine.com or contact us directly to explore this exciting career opportunity. Join us in shaping the future of hardware design and advancing your career in the field of design verification. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,

Job Title: Senior / Lead Design Verification Engineer Experience: 6 10 years Location: Siruseri, Chennai (Work from Office only) Industry: Semiconductor / VLSI Employment Type: Full-time / Permanent Key Responsibilities: Perform functional verification at block and chip level for complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs or subsystems. Develop and execute detailed verification test plans based on design specifications. Write directed and constrained-random test cases; debug simulation failures. Perform coverage analysis (functional and code) and drive closure. Work with RAL (Register Abstraction Layer) to verify register-level functionality. Develop and validate assertions (SVA) for protocol and functional correctness. Collaborate closely with RTL, DFT, and GLS teams to ensure alignment across design phases. Participate in multiple tapeouts, ensuring verification quality and delivery. Required Skills: • Strong hands-on experience with SystemVerilog and UVM methodology. • Solid knowledge of SoC/ASIC architecture and verification lifecycle. • Hands-on experience in writing testbenches, stimulus, checkers, monitors, and scoreboards . • Strong debugging skills using simulation tools like VCS, Questa. • Experience with functional and code coverage. • Familiarity with Register Abstraction Layer (RAL) modeling and verification. • Excellent analytical and problem-solving skills. • Strong communication and teamwork abilities. Interested candidates kindly forward your resume to swetha.s@thompsonshr.com