Design Verification Lead

Smart Soc Solutions

8 - 13 years

8 - 12 Lacs

Hyderabad Bengaluru

Posted:4 days ago| Platform:

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Skills Required

design verification system verilog sv uvm ethernet soc verification c++ soc vhdl rtl design axi java git rtl coding ahb perl i2c asic asic verification c ovm verilog pcie vlsi unix

Work Mode

Work from Office

Job Type

Full Time

Job Description

Experience Level: 8+ years
Location: Bangalore/Hyderabad

Skills:

Profound expertise in MACSec and Ethernet technologies.
MACSec (Media Access Control Security): Proficient in point-to-point security implementation on Ethernet links, adhering to the IEEE 802.1AE-2018 standard.
IPsec (Internet Protocol Security): Skilled in establishing security between two devices across an Internet Protocol network.
Hands-On Knowledge: Proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), with practical experience in their application.
Testbench Development: Demonstrated experience in developing comprehensive Test Benches (TB) and individual verification components.
Communication and Leadership: Possesses excellent communication skills and adept at leading and coordinating teams effectively.
Job Category VLSI (Silicon engineering)
Job Type Full Time
Job Location IndiaBangalore IndiaHyderabad

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Design Verification Lead