Lead Physical Design Engineer

• Bangalore, India
• 10+
• Full-Time
  

Lead Physical Design Engineer

Place-and-Route (PNR)

Key Responsibilities

• Lead physical design execution for flat SoC projects from RTL handoff through GDSII.
• Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS).
• Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools.
• Develop and maintain SDC constraints for PNR stages.
• Drive physical verification (DRC, LVS, antenna checks) and resolve violations.
• Perform congestion analysis and optimization for flat SoC designs.
• Work with methodology teams to improve PNR flow and scalability.
• Mentor junior engineers on PNR best practices and advanced Cadence Innovus features.
  

Qualifications

Must-Have:

• Bachelors or Masters degree in Electrical/Electronics/Computer Engineering or related field.
• 1012 years of hands-on physical design and PNR experience.
• Proven ability to handle flat SoC designs in Cadence flow
• Strong knowledge of floorplanning, CTS, routing, optimization, and sign-off closure.
• Solid understanding of STA, SDC creation, and ECO flows for physical implementation.
• Prior technical leadership or mentoring experience.
  

Nice-to-Have

• Automotive semiconductor experience
• Low-power implementation (UPF/CPF).
• Experience with scripting (Tcl, Perl, Python) for automation.