Lead Physical Design Engineer

JD for a Physical Design Lead (Sub-3 nm, TSMC, 810 yrs, Synopsys / Cadence)

Physical Design Lead Advanced Node (Sub-3 nm, TSMC)

Location:

Experience

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Position Summary

Lead end-to-end physical implementation and signoff for complex SoC blocks or subsystems at advanced nodes (5 nm, 3 nm and below), using Synopsys and/or Cadence tool flows, preferably, targeting TSMC technologies. Own PPA and signoff closure for

multi-million instance designs and drive successful production tape-outs while leading and mentoring a local PD team.

high-complexity blocks/subsystems with multi-million standard-cell instances (10M+ gate equivalent)

Synopsys PrimeTime (PT) and/or Cadence Tempus

Power Delivery Network (PDN)

IR drop and EM signoff

Mentor Calibre, Cadence Pegasus

low-power design techniques

TSMC PDKs, reference flows and tape-out processes

technical leadership

ASIC physical design experience

multi-million standard-cell instances / multi-tens-of-million gate equivalent

Strong hands-on experience with one or more of the following tool chains:

Synopsys flow:

Cadence flow:

advanced-node challenges

PDN planning and EMIR closure

Tcl and/or Python

B.E./B.Tech or M.E./M.Tech in ECE/EEE/VLSI or related discipline from a recognized institute.

Excellent communication and collaboration skills to work with cross-site, cross-functional teams; strong ownership mindset and ability to drive issues to closure under aggressive schedules.