Physical Verification Engineer Siliciom Technologies

3.0 - 7.0 years

0 Lacs

karnataka

On-site

You should have a Bachelor's or Master's degree in Engineering with 3 to 5 years of experience in Physical verification at block-level and chip-level. You must have expertise in DRC, LVS DFM, Antenna, Density Fill Routines, and other Tape-out sign-off processes. Proficiency in using Synopsys ICC Tool is required, along with tape-out experience of multiple complex chips at 14 nm or below. You should be familiar with Mentor Calibre or Synopsys ICC and ICV tools and have programming skills in tcl, Perl, or C. In this role, you will be responsible for planning and addressing electrical considerations like EM, IR, Noise, etc., throughout the design process. Exposure to physical verification flow ...

Posted 2 weeks ago

Apply

Layout Design, Engineer Synopsys Inc

2.0 - 4.0 years

0 Lacs

Bengaluru, Karnataka, India

On-site

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and meticulous engineer with a deep commitment to excellence in analog and high-speed mixed signal layout design. With a minimum of 2 years of hands-on experience in advanced technology nodes (5nm and below), you thrive in dynamic, collaborative environments w...

Posted 1 month ago

Apply

ASIC Engineering Technical Leader Cisco

10.0 - 15.0 years

12 - 17 Lacs

Bengaluru

Work from Office

Our creative and versatile Physical Design team in Bangalore, India. As a member of our physical verification team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing, design-for-yield, design-for-reliability and lithography) at the chip and block level. You will collaborate with the CAD, Foundry Operations teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on pad ring, bump, RDL design, and working with the package and floorplan teams. Technica...

Posted 3 months ago

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.