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ASIC Engineering Technical Leader

10 - 15 years

12 - 17 Lacs

Bengaluru

Posted:2 weeks ago| Platform: Naukri logo

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Skills Required

ASIC Engineering automation scripts Mentor Calibre ASIC physical design CAD RDL design Synopsys ICV

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Work from Office

Job Type

Full Time

Job Description

Our creative and versatile Physical Design team in Bangalore, India. As a member of our physical verification team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing, design-for-yield, design-for-reliability and lithography) at the chip and block level. You will collaborate with the CAD, Foundry Operations teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on pad ring, bump, RDL design, and working with the package and floorplan teams. Technical Requirements 10+ years of physical design experience with emphasis on physical verification Real chip tapeout experience in sub-nm technology nodes with a track record of successful signoff Collaborate with Process Integration, CAD and PDK teams to mitigate physical verification rule deck issues. Strong knowledge of physical verification flows and methodology Code and maintain scribe design specific Calibre DRC/LVS rule decks. Implement automation scripts in Calibre SVRF, Perl, Python, Bash and C-shell. Develop and maintain automation solutions for scribe design specific Calibre DRC/LVS. Knowledge of all aspects of ASIC physical design Scripting skills to debug flow related issues and make enhancements as appropriate Expertise in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc. Experience in planning physical verification for closure. Experience in leading and mentoring a team in physical verification. Ability to work cross-functionally with various teams and be productive under aggressive schedules.

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