Physical Verification Engineer

You should have a Bachelor's or Master's degree in Engineering with 3 to 5 years of experience in Physical verification at block-level and chip-level. You must have expertise in DRC, LVS DFM, Antenna, Density Fill Routines, and other Tape-out sign-off processes. Proficiency in using Synopsys ICC Tool is required, along with tape-out experience of multiple complex chips at 14 nm or below. You should be familiar with Mentor Calibre or Synopsys ICC and ICV tools and have programming skills in tcl, Perl, or C. In this role, you will be responsible for planning and addressing electrical considerations like EM, IR, Noise, etc., throughout the design process. Exposure to physical verification flow automation will be an added advantage. If you are interested in joining Siliciom Technologies and want to learn more about the company, please reach out to us at careers@siliciom.com.,