Physical Verification Engineer

Role Overview: You will work with floorplan and physical design engineers to drive physical verification convergence. Your proficiency in DRC and LVS analysis at advanced nodes like 5nm or below will be crucial. Having good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred. Your working knowledge on full chip phyV will be an added advantage, and prior experience on FullChip RDL like IO/PADRing routing will be preferred. Understanding multi voltage regions will also be advantageous. Key Responsibilities: - Collaborate with floorplan and physical design engineers for physical verification convergence. - Perform DRC and LVS analysis at advanced nodes like 5nm or below. - Demonstrate good knowledge in specific areas such as Antenna, ESD, ERC, LUP. - Utilize working knowledge on full chip phyV, with prior experience in FullChip RDL like IO/PADRing routing being preferred. - Understand multi voltage regions for improved performance. Qualifications Required: - B.Tech / M.Tech or equivalent from a reputed University. - 4 - 6 years of relevant experience. - Expertise in Calibre/ICV and ICC2 tools. - Scripting skills preferred, with experience in automation tools like tcl, perl, python, etc. - RDL experience. - Full chip/subsystem LV experience in layout debug and fix. - Good PV-PD knowledge.,