15 Erc Jobs

Experience Minimum 1012 years of experience in call centre operations with least 5 years in a leadership or managerial role. Proven track record in managing large-scale, 24/7 Emergency Call Center or Response Operations. Key Responsibilities o Oversee day-to-day operations of the ERC, ensuring efficiency and SLA adherence. o Develop and implement protocols for emergency call handling and dispatch services. o Coordinate with ERC Doctors, Team Leads, and IT staff to streamline workflows. o Conduct performance evaluations and provide training to enhance team efficiency. o Ensure adequate staffing levels and shift rotations for 24/7 operations. o Monitor key performance indicators (KPIs) for call handling, response times, and resource utilization. o Prepare and present performance reports to senior management. o Ensure service quality by monitoring calls, reviewing reports, and addressing complaints. o Work with the Quality & Training team to conduct regular training sessions and audits. o Coordinate with external stakeholders, medical teams and government agencies, during critical incidents. o Develop and execute contingency plans for ERC operations. o Manage ERC budgets, ensuring cost efficiency in operations. o Ensure compliance with legal, regulatory, and contractual obligations. o Maintain all records of operations, performance metrics, and incidents for audits & reporting. Prepared by- Pradeep Reddy, Project Manager, Sumeet SSG, India. Key Skills o Strong leadership and operational management skills. o Proficiency in call centre technologies and emergency response protocols. o Excellent communication, crisis management, and decision-making ability.

Looking for profiles with up to 10 years of experience as an Insurance Business Analyst. Key requirements include a strong background in Property and Casualty (P&C) Insurance for both Personal and Commercial lines. It is essential to have a deep understanding of ISO products, specifically Electronic Rating Content (ERC) and their functionalities. Contract: Remote Budget: Open Location india

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping out high-performance microcontroller chips and collaborate with cross-functional teams including Chip team, Tech, and CAD. Developing scripts and methods for layout design automation will also be a part of your duties. Onsemi is dedicated to driving disruptive innovations in automotive and industrial markets to create a better future. The company focuses on megatrends like vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a unique product portfolio, Onsemi develops intelligent power and sensing technologies to address complex global challenges and lead the way in building a safer, cleaner, and smarter world. Minimum qualifications for this role include a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience. Preferred candidates should have experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies. Proficiency in interpreting CALIBRE DRC, ERC, LVS reports, programming skills in SKILL, Perl, and/or Python, and experience with CADENCE or MENTOR GRAPHICS layout tools are desirable. Strong understanding of semiconductor manufacturing process, DFM techniques, and familiarity with Cadence Design Environment (CDE) and Unix OS are also required. Effective communication skills and a collaborative team spirit are essential for success in this role.,

As a Physical Verification Engineer at Alphawave Semi, you will play a crucial role in accelerating data communication for the digital world of tomorrow. Your responsibilities will revolve around implementing Physical Verification processes with a focus on project completion and tapeout activities. You will be tasked with owning and executing the Physical Verification flow, showcasing expertise in analyzing and resolving issues related to DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck using tools like Calibre/ICV. Collaborating closely with the PD team, you will address PV challenges and contribute to SoC-level PV sign-off checks. To excel in this role, you should bring to the table at least 10 years of experience in Physical Verification, along with a strong background in checks such as DRC, LVS, Antenna, ERC, PERC, ESD using Calibre/ICV. Your proficiency in debugging and rectifying issues related to base DRC, metal DRC, particularly in advanced process nodes, will be essential. Hands-on experience in fixing DRC/LVS in environments like Innovus/Fusion Compiler is a must, along with expertise in LVS/antenna debugging and runtime reduction techniques. Additionally, you should possess scripting skills in Unix, Perl, Python, SVRF, and Tcl to facilitate timely tapeouts, and a solid understanding of full chip integration and flows would be advantageous. At Alphawave Semi, we prioritize the well-being and growth of our employees. We offer a flexible work environment that supports personal and professional development. In addition, you will benefit from a comprehensive compensation package, including Restricted Stock Units (RSUs), opportunities for advanced education from premium institutes and eLearning providers, medical insurance, wellness benefits, educational assistance, advance loan support, and office lunch and snacks facilities. Alphawave Semi is committed to fostering a diverse and inclusive workplace. We are an equal opportunity employer that values diversity and provides accommodations throughout the recruitment process to ensure all applicants have an equal opportunity to thrive, irrespective of age, gender, race, disability, or other protected characteristics.,

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

As an I/O Layout Design Engineer, you will be responsible for custom layout development from block level to top level I/O layout for various interfaces such as GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS, etc. You should have knowledge of Latchup, ESD, and EM considerations, especially in lower nodes like 3nm and 5nm. Your skills will be tested in performing tasks such as LVS/DRC/ERC/Litho Checks, Antenna, ESD-LU, Density checks. It is essential to have a deep understanding of CMOS functionality, CMOS fabrication processes, different foundries, and the challenges posed by the latest technology nodes. Proficiency in industry-standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber, etc., is a must. Your problem-solving abilities, logical reasoning skills, and effective communication skills will be vital for this role. Ideally, you should have a minimum of 4 to 7 years of experience in this field. The location for this position is Electronic City, Bangalore, and the expected joining date is within 2 to 4 weeks.,

You will be responsible for developing block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Your role will involve applying an understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues. It is essential to stay abreast of new verification methods and work collaboratively with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. To qualify for this position, you must have a Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or a related field and a minimum of 2 years of experience designing custom layouts in a relevant domain. Alternatively, an Associate's degree in a related field with 4+ years of experience or a High School diploma with 6+ years of relevant experience will also be considered. Additionally, you should have at least 2 years of experience using layout design and verification tools such as cadence, LVS, and rmap. Qualcomm India Private Limited is a company of inventors seeking to revolutionize the CPU market. As an SRAM Mask Layout Designer, you will have the opportunity to work with a highly talented team to create designs that push the envelope on performance, energy efficiency, and scalability. The role involves developing block or macro level layouts and floorplans for high-performance custom memories based on project requirements and design schematics. Preferred qualifications for this role include a good understanding of device parasitics and reliability considerations during layout, knowledge of leading-edge processes, experience in layout design of library cells and memories in deep sub-micron technologies, and proficiency in industry-standard custom design tools and flows. Good communication skills are essential to work effectively with different teams and accurately describe issues. Key responsibilities include designing layout for custom memories and digital circuits, reading and interpreting design rule manuals, owning the entire layout process from floorplanning to physical verification, and providing insight into strategic decisions regarding memory layout. You should be able to work independently, execute memory layout with minimal supervision, and provide realistic schedules for layout completion. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. It is important to abide by all applicable policies and procedures, including security and confidentiality requirements.,

You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies You thrive in dynamic environments and possess a strong problem-solving aptitude With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills Your commitment to diversity and inclusion aligns with Synopsysvalues, and you are eager to work in an environment that welcomes all perspectives, What Youll Be Doing: Hands-on development of layout for next-generation DDR/HBM/UCIe IPs, Solving complex problems and debugging issues effectively, Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements, Ensuring compliance with DRC, LVS, ERC, and antenna rules, Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below), Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, The Impact You Will Have: Enhancing the performance and reliability of SynopsysDDR/HBM/UCIe IPs, Accelerating the integration of advanced capabilities into SoCs, Reducing risk and improving time-to-market for differentiated products, Driving innovation in semiconductor technology and design, Contributing to the success of SynopsysSilicon IP business, Fostering a collaborative and inclusive work environment, What Youll Need: BTech/MTech degree in a relevant field, 4+ years of experience in analog layout design, Proven track record in developing high-quality layouts and meeting verification timelines, Strong understanding of deep submicron effects and floorplan techniques, Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation, Who You Are: Detail-oriented with excellent problem-solving skills, Collaborative and able to foster accountability and ownership, Strong written, verbal communication, and interpersonal skills, Committed to diversity and inclusion, The Team Youll Be A Part Of: You will be part of a dynamic team focused on developing next-generation DDR/HBM/UCIe PHY IPs Our team values innovation, collaboration, and continuous improvement, driving the success of SynopsysSilicon IP business, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and top levels for industry-leading CPU core designs, emphasizing scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Working on cutting-edge technology nodes and applying advanced physical design techniques to enhance CPU performance and efficiency is a key aspect of this role. Key responsibilities include driving floorplan architecture and optimization in collaboration with PD/RTL teams, engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams, partnering with EDA tool vendors and internal CAD teams for improved design efficiency, making strategic trade-offs in design decisions to achieve optimal PPA outcomes, and ensuring end-to-end Physical verification closure for subsystem. The ideal candidate will have experience in physical design including floor-planning, placement, clock implementation, and routing for complex, big, and high-speed designs. Knowledge of physical synthesis and implementation tools such as Cadence Innovus/Genus and Synopsys Fusion Compiler is preferred, along with a good understanding of CMOS circuit design, static timing analysis, reliability, and power analysis. Strong collaboration skills, innovative thinking for power and performance improvements, scripting skills, and expertise in Physical Verification flow are required. Preferred skills for this role include clock implementation, power delivery network design choices, process technology knowledge, experience in flow and methodology development, hands-on experience with Synthesis, DFT, Place and Route, and Timing and Reliability Signoff. Interaction with design and architecture teams, working with sub-micron technology process nodes, and prior experience in flow and methodology development are advantageous. Minimum qualifications include a Bachelor's degree in Electrical/Computer Engineering, 8+ years of direct top-level floor-planning experience, a strong background in VLSI design, physical implementation, and scripting, as well as experience working with industry-standard Synthesis and Place and Route tools. Self-motivation, time management skills, and a commitment to abide by all applicable policies and procedures are expected from applicants. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floorplanning is a plus. Show more Show less

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

Role & responsibilities Respond to customer HR inquiries through multiple channels - Phone, chat and web tickets.(calls, webforms, emails, chats and voicemails). Develop an understanding of US Human Capital Management (HCM) nuances, including payroll, benefits, talent, policies etc. Gain hands-on experience with applications like Workday, Oracle, SAP, and UKG. Developing a higher level of accuracy and speed in task completion, demonstrating the ability to efficiently process transactions, showing proficiency in client service Communicate (verbal and written) with customers from different countries and cultures. Utilize the client knowledge base to find answers and solutions independently Own incidents/issues end to end with minimum guidance. Understanding and adherence to contractual goals and Service Level Agreements (SLAs) Document recurring and known service request resolutions in the knowledge base. Demonstrate flexibility in working in different shifts (24x7 operations). Developing a high level of accuracy and speed in task completion, demonstrating the ability to efficiently close tickets, showing proficiency in client service

Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Good understanding of PD flows and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and DRV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. Interested candidates can share their resumes to shubhanshi@incise.in

Analog layout design requires knowledge of designing layouts of complex VLSI (very large scale integration) circuits using graphic editing tools in the Analog domain. A major portion of the job is in the creation of new physical design data from concepts, partial schematics, or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Your Role and Responsibilities Hands-on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below , and also take leadership roles in delivery of IPs. Work on Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimizations . Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. Participate in building and enhancing layout flow for faster, higher quality design process. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks. Collaborate with Circuit Designers to solve challenging problems. Writing SKILL/PYTHON scripts to automate repetitive tasks. Work with Place and Route engineer to integrate custom macros into the top level. Able to perform design reviews across global teams. Work closely with required global teams to ensure the success of the whole product. Leadership in delivery of macros we plan to own from India. Job Requirements Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers , etc. Experience in designing layouts for high-speed circuits is a plus. Layout experience in the following technology nodes: 3nm, 5nm, and 7nm FinFET . Good team worker with multi-discipline, multi-cultural, and multi-site environments. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability, and failure mechanisms. Good problem-solving skills are essential where problems are analyzed upfront, identifying gaps, and providing optimum solutions. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required Education Bachelor's Degree Preferred Education Master's Degree Required Technical and Professional Expertise The Analog layout design engineer with experience in next-generation Ultra high-speed serial IO link (HSS) interface for Cognitive, ML, DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high-speed 32G/50G/112G IO link interfaces . Preferred Technical and Professional Experience Experience in 7 and 14 nm analog layout design . Working on Cutting edge technology and HSS domain. Quick learner, deep layout design knowledge, problem-solving skills, and good communication skills with cross teams across the Geos.

Key Skills: Netlist to GDSII flow, CTS, timing closure DRC, LVS, PERC, ERC, Soft Checks Tools: Innovus, ICC, PrimeTime, Calibre, Redhawk Worked on 28nm & below nodes Strong debugging and custom routing skills.