46 Erc Jobs

Role Overview: You will work with floorplan and physical design engineers to drive physical verification convergence. Your proficiency in DRC and LVS analysis at advanced nodes like 5nm or below will be crucial. Having good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred. Your working knowledge on full chip phyV will be an added advantage, and prior experience on FullChip RDL like IO/PADRing routing will be preferred. Understanding multi voltage regions will also be advantageous. Key Responsibilities: - Collaborate with floorplan and physical design engineers for physical verification convergence. - Perform DRC and LVS analysis at advanced nodes like 5nm or below. -...

As a Physical Verification Engineer for SOC/blocks, your role will involve the following key responsibilities: - Conduct physical verification for SOCs, cores, and blocks, encompassing tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. - Tackle critical design and execution challenges related to physical verification and sign-off. - Possess a thorough understanding of physical verification and sign-off workflows and methodologies. - Collaborate with PNR engineers to attain sign-off at different stages of the design process. To excel in this role, you should have the following qualifications and skills: - Proficiency in physical verification for SoC/full-chip and block-level proces...

You have the opportunity to work as an Analog / Mixed Signal Layout Designer with 2-8 years of hands-on experience in advanced FinFET processes such as 16nm, 12nm, 10nm, 7nm, 5nm, 3nm. Your responsibilities will include: - Expertise in complete PNR flow including CTS, routing, and Timing Closure. - Hands-on experience in critical blocks like SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. - Understanding of CMOS / Bi-CMOS / SOI / FinFET process and AMS IP integration according to Full Chip needs. - Problem-solving skills in Routing Congestion, Physical Verification in Custom Layout, and verification checks...

As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification, and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To: - Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. - Proactively identify problem areas for improvement, propose, and develop innovative solutions. - Develop...

Physical Verification Engineers Experience : 3 years Location : Bangalore Will be responsible for Runing Physical verification analysis for multiple designs, analyzing results and providing fixes to address the issues for complex cpu designs, in latest technology nodes. n (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical Design (PD), RTL, and CAD teams to resolve PV issues and ensure sign-off quality. Analyze and debug PV violations using Calibre tool and provide fixes to be taken using PnR tools like Innovus Understanding of all Physical verification signoff checks Understanding of DRC/LVS/ANTENNA for latest technology nodes and solving the issues Basic ...

As an experienced Analog Layout design engineer, you should possess qualities such as innovation, collaboration, meticulousness, and curiosity. You will be responsible for: - Layout of basic digital and analog building blocks using analog transistor level components - Layout of analog macros, power pads, and input/output pads utilizing the above blocks - Working closely with Analog designers in floorplanning, power grid, and signal flow planning - Conducting physical and electrical verification including DRC, LVS, EM/IR, ERC, PERC Latch up, and PERC ESD - Creating blackbox models for other groups in the design flow Preferred experience includes: - Detailed knowledge of CMOS circuit theory - ...

Role & responsibilities * Candidate should be having a Bachelors degree in electrical engineering with minimum 5+ years of experience in Physical Verification * Hands on debugging skills in different physical verification checks like LVS,DRC,ERC,PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools. * Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. * Working experience in cutting edge technologies such as 5nm, 7nm and 16ff process nodes is desire Location-Bangalore

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X). Job Description: Principal Digital Physical Design Engineer Role Overview A Princ...

Company Qualcomm India Private Limited Job Area Engineering Services Group, Engineering Services Group > Layout Engineer General Summary Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, an...

Company Qualcomm India Private Limited Job Area Engineering Services Group, Engineering Services Group > Layout Engineer General Summary Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, an...

As an IO Layout Engineer at our company, you will play a crucial role in the layout design of IO blocks such as GPIO, Analog IOs, High-Speed IOs, and Pad ring. Your responsibilities will include: - Working on IO layout for ASIC controllers under the guidance of senior team members. - Collaborating closely with designers to understand design constraints and create quality layout efficiently. - Managing all the Sign Off PV & quality checks on an IP layout. To excel in this role, you are required to meet the following qualifications and requirements: - Hold a Bachelor's or Master's degree in Electronics & Communication/Electrical engineering. - Possess 4 to 8 years of working experience in IO l...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwid...

8+ years of experience in Layout automation, Physical Verification, or related domains. Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity. Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc. Working experience in PDN analysis tools like Totem/VoltusXFA/XA is preferable. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus. Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC...

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most?innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they?provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are?the same. Job Description Your Role As a Memory/Custom Layout Design Engineer, you will be responsible for designing high-performance memory leafcell layout libraries from scratch and integrating them at ...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experienceprimarily in Physical Verification (PV)you thrive on solving complex layout and verifica...

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routability analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with Caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes...

As a Physical Verification Engineer, you will be responsible for the following: - Hands-on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD, and DFM using tools such as Calibre, ICV, and Pegasus PV. - Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. - Working experience in cutting-edge technologies such as 3/4/5nm and 7nm process nodes is desired. Qualifications required for this role: - B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent. Please note that the job location for this role is Bangalore, Hyderabad, or Noida.,

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, including circuits, mechanical systems, and digital/analog/RF/optical systems. Your role will involve working on cutting-edge products, collaborating with cross-functional teams, and meeting performance requirements. The Qualcomm Noida CPU team is specifically looking for individuals to handle the hardening of complex HMs from RTL to GDS, including synthesis, PNR, and timing. - Develop high-performance and power-optimized custom CPU cores - Physical verification post BTECH / MTECH with at least 5 years of experience - Exper...

As a Physical Verification Engineer, you will be responsible for performing layout verification of integrated circuits (ICs) using industry-standard tools. Your role will include checking for DRC, LVS, ERC, and other checks to ensure the design is manufacturable and compliant with foundry rules. Key Responsibilities: - Perform layout verification of ICs using industry-standard tools - Check for DRC, LVS, ERC, and other verification checks - Ensure the design is manufacturable and compliant with foundry rules Qualifications Required: - 4-7 years of experience in physical verification of IC layout - Proficiency in industry-standard physical verification tools - Strong understanding of DRC, LVS...

ANALOG LAYOUT ENGINEER An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious. KEY RESPONSIBILITIES: Layout of basic digital and analog building blocks using analog transistor level components. Layout of analog macros, power pads, and input/output pads using above blocks Working closely with Analog designers in floorplanning; power grid and signal flow planning Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD Creation of blackbox models for other groups in the design flow PREFERRED EXPERIENCE: Must have detailed knowledge of CMOS circuit theory. Must have ability to communicate with various teams ...

Key Responsibilities: Perform physical verification at the SoC, core, and block levels, including DRC, LVS, ERC, ESD, DFM, and tapeout tasks. Address complex physical design challenges related to sign-off and ensure timely resolution. Maintain deep understanding of physical verification workflows and methodologies across RTL to GDS2. Collaborate with Place-and-Route (PNR) teams to support verification sign-offs at various stages. Troubleshoot and resolve LVS issues, particularly for complex analog-mixed signal IP integrations. Support verification of full-chip components including I/O rings, corner cells, seal rings, RDL routing, and bumps. Contribute to the development of sign-off methodolo...

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profile Experienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and FinFET node implementation.

Company Description Thalia is a venture-funded technology business with facilities in Cwmbran, United Kingdom; Hyderabad, India; and Cologne, Germany. The company provides analog and mixed signal design solutions for integrated circuit (IC) manufacturers and IP companies utilizing unique design automation technology and strong value-added services capabilities. With support from investors like Mercia Fund Management and Finance Wales, along with grants from Innovate UK and The Welsh Government, Thalia enables customers to migrate designs, generate portfolios, and develop faster IPs, achieving reduced design cycles, lower costs, and shorter time to market. Thalia has successfully delivered nu...

Hi All, Title : Analog Layout Engineer Exp Level:3+ yrs Location: Bangalore Job Description: Design and development of full custom analog/mixed-signal layout at block and top level. Strong expertise in analog layout techniques for circuits such as ADC, DAC, PLL, LDO, Bandgap, etc. Hands-on experience with layout tools like Cadence Virtuoso, Calibre, and Mentor tools. Ensure layout meets DRC, LVS, ERC, Antenna, and other physical verification requirements. Work closely with circuit design engineers to plan, review, and optimize layout. Experience in advanced process nodes (e.g., 7nm, 5nm, 3nm) preferred. Understanding of EMIR, ESD, and reliability requirements Proficient in hierarchical and f...

As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification, and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To: - Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. - Proactively identify problem areas for improvement, propose, and develop innovative solutions. - Develop...