30 Erc Jobs

As a Physical Verification Engineer, you will be responsible for the following: - Hands-on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD, and DFM using tools such as Calibre, ICV, and Pegasus PV. - Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. - Working experience in cutting-edge technologies such as 3/4/5nm and 7nm process nodes is desired. Qualifications required for this role: - B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent. Please note that the job location for this role is Bangalore, Hyderabad, or Noida.,

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, including circuits, mechanical systems, and digital/analog/RF/optical systems. Your role will involve working on cutting-edge products, collaborating with cross-functional teams, and meeting performance requirements. The Qualcomm Noida CPU team is specifically looking for individuals to handle the hardening of complex HMs from RTL to GDS, including synthesis, PNR, and timing. - Develop high-performance and power-optimized custom CPU cores - Physical verification post BTECH / MTECH with at least 5 years of experience - Exper...

As a Physical Verification Engineer, you will be responsible for performing layout verification of integrated circuits (ICs) using industry-standard tools. Your role will include checking for DRC, LVS, ERC, and other checks to ensure the design is manufacturable and compliant with foundry rules. Key Responsibilities: - Perform layout verification of ICs using industry-standard tools - Check for DRC, LVS, ERC, and other verification checks - Ensure the design is manufacturable and compliant with foundry rules Qualifications Required: - 4-7 years of experience in physical verification of IC layout - Proficiency in industry-standard physical verification tools - Strong understanding of DRC, LVS...

ANALOG LAYOUT ENGINEER An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious. KEY RESPONSIBILITIES: Layout of basic digital and analog building blocks using analog transistor level components. Layout of analog macros, power pads, and input/output pads using above blocks Working closely with Analog designers in floorplanning; power grid and signal flow planning Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD Creation of blackbox models for other groups in the design flow PREFERRED EXPERIENCE: Must have detailed knowledge of CMOS circuit theory. Must have ability to communicate with various teams ...

Key Responsibilities: Perform physical verification at the SoC, core, and block levels, including DRC, LVS, ERC, ESD, DFM, and tapeout tasks. Address complex physical design challenges related to sign-off and ensure timely resolution. Maintain deep understanding of physical verification workflows and methodologies across RTL to GDS2. Collaborate with Place-and-Route (PNR) teams to support verification sign-offs at various stages. Troubleshoot and resolve LVS issues, particularly for complex analog-mixed signal IP integrations. Support verification of full-chip components including I/O rings, corner cells, seal rings, RDL routing, and bumps. Contribute to the development of sign-off methodolo...

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profile Experienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and FinFET node implementation.

Company Description Thalia is a venture-funded technology business with facilities in Cwmbran, United Kingdom; Hyderabad, India; and Cologne, Germany. The company provides analog and mixed signal design solutions for integrated circuit (IC) manufacturers and IP companies utilizing unique design automation technology and strong value-added services capabilities. With support from investors like Mercia Fund Management and Finance Wales, along with grants from Innovate UK and The Welsh Government, Thalia enables customers to migrate designs, generate portfolios, and develop faster IPs, achieving reduced design cycles, lower costs, and shorter time to market. Thalia has successfully delivered nu...

Hi All, Title : Analog Layout Engineer Exp Level:3+ yrs Location: Bangalore Job Description: Design and development of full custom analog/mixed-signal layout at block and top level. Strong expertise in analog layout techniques for circuits such as ADC, DAC, PLL, LDO, Bandgap, etc. Hands-on experience with layout tools like Cadence Virtuoso, Calibre, and Mentor tools. Ensure layout meets DRC, LVS, ERC, Antenna, and other physical verification requirements. Work closely with circuit design engineers to plan, review, and optimize layout. Experience in advanced process nodes (e.g., 7nm, 5nm, 3nm) preferred. Understanding of EMIR, ESD, and reliability requirements Proficient in hierarchical and f...

As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification, and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To: - Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. - Proactively identify problem areas for improvement, propose, and develop innovative solutions. - Develop...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwid...

As an experienced Analog Layout design engineer, you are expected to be innovative, collaborative, meticulous, and curious. Key Responsibilities: - Layout of basic digital and analog building blocks using analog transistor level components. - Layout of analog macros, power pads, and input/output pads using the above blocks. - Working closely with Analog designers in floorplanning; power grid and signal flow planning. - Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up, and PERC ESD. - Creation of blackbox models for other groups in the design flow. Preferred Experience: - Must have detailed knowledge of CMOS circuit theory. - Must have the ability to communicat...

As a Physical Verification Engineer for SOC/blocks, your role involves performing physical verification for SOCs, cores, and blocks, which includes tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. You will be responsible for addressing critical design and execution challenges related to physical verification and sign-off. It is essential for you to have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Collaboration with PNR engineers to achieve sign-off at various stages of the design process is also a key aspect of your role. Your qualifications and skills should include proficiency in physical verification for SoC/full-chip and b...

Job Description: 3-8 years of experience in Memory/Custom Layout design. Memory Leaf cell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Good Knowledge in EM and IR run and fix. Proficient in Cadence Virtuoso layout editor and Caliber physical verification flow

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. This position will focus on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with an emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities: - Drive floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA - Engage in cross-fun...

Job Description: 3-8 years of experience in Memory/Custom Layout design. Location: Bangalore Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Good Knowledge in EM and IR run and fix. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow

Experience Minimum 1012 years of experience in call centre operations with least 5 years in a leadership or managerial role. Proven track record in managing large-scale, 24/7 Emergency Call Center or Response Operations. Key Responsibilities o Oversee day-to-day operations of the ERC, ensuring efficiency and SLA adherence. o Develop and implement protocols for emergency call handling and dispatch services. o Coordinate with ERC Doctors, Team Leads, and IT staff to streamline workflows. o Conduct performance evaluations and provide training to enhance team efficiency. o Ensure adequate staffing levels and shift rotations for 24/7 operations. o Monitor key performance indicators (KPIs) for cal...

Looking for profiles with up to 10 years of experience as an Insurance Business Analyst. Key requirements include a strong background in Property and Casualty (P&C) Insurance for both Personal and Commercial lines. It is essential to have a deep understanding of ISO products, specifically Electronic Rating Content (ERC) and their functionalities. Contract: Remote Budget: Open Location india

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping o...

As a Physical Verification Engineer at Alphawave Semi, you will play a crucial role in accelerating data communication for the digital world of tomorrow. Your responsibilities will revolve around implementing Physical Verification processes with a focus on project completion and tapeout activities. You will be tasked with owning and executing the Physical Verification flow, showcasing expertise in analyzing and resolving issues related to DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck using tools like Calibre/ICV. Collaborating closely with the PD team, you will address PV challenges and contribute to SoC-level PV sign-off checks. To excel in this role, you should bring to the table at lea...

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL de...

As an I/O Layout Design Engineer, you will be responsible for custom layout development from block level to top level I/O layout for various interfaces such as GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS, etc. You should have knowledge of Latchup, ESD, and EM considerations, especially in lower nodes like 3nm and 5nm. Your skills will be tested in performing tasks such as LVS/DRC/ERC/Litho Checks, Antenna, ESD-LU, Density checks. It is essential to have a deep understanding of CMOS functionality, CMOS fabrication processes, different foundries, and the challenges posed by the latest technology nodes. Proficiency in industry-standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber, et...

You will be responsible for developing block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Your role will involve applying an understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues. It is essential to stay abreast of new verification methods and work collaboratively with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. To qualify for this posi...

You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies You thrive in dynamic environments and possess a strong problem-solving aptitude With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills Your commitment to diversity and inclusion aligns with Synopsysvalues, and you are eager to work in an environment that welcomes all persp...

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and...

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. Comprehensive experience and understanding of all stages of t...