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4.0 - 8.0 years
0 Lacs
telangana
On-site
Role Overview: You will work with floorplan and physical design engineers to drive physical verification convergence. Your proficiency in DRC and LVS analysis at advanced nodes like 5nm or below will be crucial. Having good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred. Your working knowledge on full chip phyV will be an added advantage, and prior experience on FullChip RDL like IO/PADRing routing will be preferred. Understanding multi voltage regions will also be advantageous. Key Responsibilities: - Collaborate with floorplan and physical design engineers for physical verification convergence. - Perform DRC and LVS analysis at advanced nodes like 5nm or below. -...
Posted 6 days ago
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