Mobiveil Technologies (India) A GlobalLogic We are #Looking for # Senior #Verification Engineer @ #Pune Maharashtra Exp : #8+ Years. please share your #Updated CV . & Please #help me with #references. k.keerthi@mobiveil.co.in keerthi.kotha@globallogic.com Job Description : Strong in SV and UVM with IP Level experience.
12+ years of experience with a Bachelors'/ Master's degree in the field of Electrical, Electronics, or computer engineering Should have a good understanding of verification flow, challenges, and requirements of functional verification. Have worked on IP level or Block level or SoC level functional verification. Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy. Expert in System Verilog, Verilog, and OVM/UVM verification methodology. Have working experience on AMBA interface protocols Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must. Experience with Perl, Python or similar scripting languages will be helpful.
Company Description Mobiveil Technologies Inc. is a rapidly growing technology company specializing in the creation of Intellectual Properties, frameworks, and solutions for the Networking, Storage, Consumer, Enterprise, and Device Mobility markets. Leveraging decades of experience, Mobiveil delivers high-quality, high-speed serial interconnect Silicon IP cores and custom and standard form factor hardware boards to customers globally. With dedicated integration support, flexible business models, and strong industry presence, Mobiveil solutions offer significant value to customers' marketing and engineering goals. The company is headquartered in Silicon Valley, with engineering centers in Milpitas, CA, Chennai, Bangalore, Hyderabad, and Rajkot, India, and sales offices worldwide. Role Description This is a full-time Physical Verification Engineer role located in Chennai with a hybrid work model, allowing some work from home. The Physical Verification Engineer will be responsible for performing physical verification tasks, including DRC, LVS, and ERC checks, debugging verification issues, and ensuring compliance with design rules. Additionally, the role includes collaboration with design teams to achieve tapeout schedules and providing feedback on design improvements. Qualifications Experience with DRC, LVS, and ERC checks, debugging verification issues Proficiency in EDA tools like Calibre, Assura, Hercules Knowledge of semiconductor device physics and fabrication process Strong analytical and problem-solving skills Effective communication and teamwork abilities Experience with automation scripting using Perl, Python, or TCL Bachelor's or Master's degree in Electrical Engineering or a related field