Senior Design Verification Engineer

12 years

0 Lacs

Posted:2 days ago| Platform: Linkedin logo

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On-site

Job Type

Full Time

Job Description

  • 12+ years of experience with a Bachelors'/ Master's degree in the field of Electrical, Electronics, or computer engineering
  • Should have a good understanding of verification flow, challenges, and requirements of functional verification.
  • Have worked on IP level or Block level or SoC level functional verification.
  • Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy.
  • Expert in System Verilog, Verilog, and OVM/UVM verification methodology.
  • Have working experience on AMBA interface protocols
  • Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must.
  • Experience with Perl, Python or similar scripting languages will be helpful.

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