Senior Design Verification Engineer

Company Description

KriSemi Design Technologies LLC is a leading service provider to semiconductor and EDA companies, specializing in Physical Design, Physical Verification, Analog and Mixed Signal Design, and Embedded Systems. We focus on transformative and trending technologies, addressing key challenges in the VLSI domain with innovative solutions. Our vision is to be recognized as a top semiconductor services organization, known for exceptional client service, employee satisfaction, and strong core values. Committed to quality and customer trust, KriSemi Tech collaborates with leading semiconductor design companies, driving consistent growth and success in the industry. Key expertise areas include RTL design and verification, DFT, software solutions, and turnkey projects.

Role Description

IP/Sub-System blocks

Qualifications

• Protocol Ownership:

  Take complete ownership of the verification environment, test plan, and coverage closure for blocks interfacing with

  PCIe (Gen4/Gen5/Gen6)

  and

  DDR (DDR4/DDR5/LPDDR)

  protocols.

• Testbench Development:

  Architect, design, and implement advanced verification environments (Testbenches) using

  SystemVerilog

  and

  UVM (Universal Verification Methodology)

  .

• Test Plan Creation:

  Define, document, and implement comprehensive verification test plans based on design specifications, including directed, constrained-random, and stress test scenarios.

• Functional & Performance Verification:

  Develop complex sequences, drivers, monitors, and scoreboards to verify functional correctness, performance metrics, and adherence to protocol specifications (e.g., PCIe TLP/DLLP transaction layers, DDR command/timing checks).

Analysis & Closure

Coverage Closure:

Debug & Root Cause Analysis:

Formal Verification:

• Education:

  Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

• Core DV Expertise:

  5+ years of hands-on experience in ASIC/FPGA Design Verification.

• Protocol Expertise:

  Mandatory deep knowledge and proven experience

  in verifying complex designs using

  PCIe (Gen3/4/5 or higher)

  and

  DDR/LPDDR protocols

  (DDR4/DDR5).

• Languages:

  Expert proficiency in

  SystemVerilog

  and familiarity with RTL languages (Verilog/VHDL).

• Methodology:

  Strong hands-on experience with the

  UVM

  methodology, including developing reusable Verification Components (UVCs), sequences, and hierarchical testbenches.

• Scripting:

  Proficiency in scripting languages such as

  Python, Perl, or TCL

  for test automation, environment setup, and data analysis.

• Tools:

  Hands-on experience with industry-standard EDA tools for simulation (e.g.,

  Synopsys VCS, Cadence Xcelium, Siemens Questa

  ), debugging (

  Verdi

  ), and formal verification.