Lead Physical Design Engineer Blueberry Semiconductors

8.0 - 12.0 years

0 Lacs

bengaluru, karnataka, india

On-site

JD for a Physical Design Lead (Sub-3 nm, TSMC, 810 yrs, Synopsys / Cadence) Job Title Physical Design Lead Advanced Node (Sub-3 nm, TSMC) Location: Bangalore Experience : 8+ to 12 years Job Mode : Full Time Position Summary Lead end-to-end physical implementation and signoff for complex SoC blocks or subsystems at advanced nodes (5 nm, 3 nm and below), using Synopsys and/or Cadence tool flows, preferably, targeting TSMC technologies. Own PPA and signoff closure for multi-million instance designs and drive successful production tape-outs while leading and mentoring a local PD team. Key Responsibilities Own complete physical design flow (floor planning, power planning, placement, CTS, routing,...

Posted 1 week ago

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Reliability Verification Technical Manager Intel Corporation

5.0 - 10.0 years

0 Lacs

bengaluru, karnataka, india

On-site

As part of the Design Technology Platform Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies, Enablement, Validation and Foundry Certifications of Industry Standard EDA Reliability (EM/IR); ESD Perc tools and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools. Direct reportin...

Posted 2 months ago

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