3 Congestion Analysis Jobs

As an individual responsible for modelling supply, demand, and grid congestion in US electricity markets for trading and long-term trend analysis, you will utilize power flow optimization and electrical engineering techniques to support trading decisions and system modeling, using tools such as Power World and PSSE. Conducting congestion analysis, outage distribution, and contingency analysis will also be part of your tasks. You will need to assess the impact of transmission upgrades and generation interconnections on grid congestion and market prices, as well as track electricity prices and effectively communicate market conditions to the trading team. To excel in this role, you are required to hold a Master's degree in electrical engineering, with a focus on power systems being preferred. Experience with production cost modelling software like PowerWorld and ETAP is considered advantageous. Proficiency in advanced technology skills for data-mining, including knowledge of SQL programming, is beneficial. Your ability to create compelling and analytical data visualizations using software tools like Tableau, Power BI, Excel, or others is essential. Strong coding skills in Python or MATLAB are necessary, with relevant coding experience in the field of power systems being preferred. Additionally, being a team-oriented and collaborative individual is important for success in this role. This is a full-time position with benefits such as a flexible schedule, provided food, health insurance, life insurance, paid sick time, and paid time off. The work schedule is Monday to Friday in the UK shift with weekend availability. Performance bonuses and yearly bonuses are also part of the compensation package. Candidates must be able to commute or relocate to Vadodra, Gujarat, with a requirement of at least a Bachelor's degree in electrical engineering. A minimum of 1 year of experience in electrical engineering is preferred for this role.,

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages. Drive physical verification (DRC, LVS, antenna checks) and resolve violations. Perform congestion analysis and optimization for flat SoC designs. Work with methodology teams to improve PNR flow and scalability. Mentor junior engineers on PNR best practices and advanced Cadence Innovus features. Qualifications Must-Have: Bachelors or Masters degree in Electrical/Electronics/Computer Engineering or related field. 1012 years of hands-on physical design and PNR experience. Proven ability to handle flat SoC designs in Cadence flow Strong knowledge of floorplanning, CTS, routing, optimization, and sign-off closure. Solid understanding of STA, SDC creation, and ECO flows for physical implementation. Prior technical leadership or mentoring experience. Nice-to-Have Automotive semiconductor experience Low-power implementation (UPF/CPF). Experience with scripting (Tcl, Perl, Python) for automation. Show more Show less

As a Principal Physical Design Engineer focusing on New Product Development in Power Management at OnSemi in Bengaluru, India, you will play a crucial role in the development of Power management products for various applications such as consumer, industrial, and automotive sectors. Your responsibilities will include leading the P&R process, power planning, floor planning, clock tree building, congestion analysis for complex multi-power domain designs, and continuously seeking improvements in existing flows and methods to enhance Performance, Power, and Area (PPA) metrics. Your role will require strong problem-solving skills with a deep understanding of technical issues, allowing you to collaborate effectively with both analog and digital technical staff members. You should possess a comprehensive understanding of the end-to-end digital design flow and have hands-on experience in IR & power analysis tools and flows. Proficiency in Verilog, TCL, and Perl/Python programming languages is essential for this position. Onsemi, a company focused on driving disruptive innovations in automotive and industrial end-markets, aims to create intelligent power and sensing technologies to address complex global challenges. The company's innovative product portfolio contributes to building a safer, cleaner, and smarter world by leveraging megatrends like vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. To qualify for this role, you should hold a Bachelor's degree in Electrical Engineering or a related field with at least 8 years of experience, or a Master's degree with 7 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. Your expertise should cover RTL design, ASIC synthesis, timing analysis, CDC, P&R, and UPF methodologies. Additionally, a proven track record of releasing complex ICs to the market and excellent cross-functional communication skills are required to succeed in this position. At Onsemi, we are dedicated to attracting high-performance innovators and providing a positive recruitment experience for all candidates, reflecting our commitment to being a great place to work. If you are passionate about driving innovation in Power Management and contributing to a better future, we encourage you to join our dynamic team and be part of our journey towards creating a more sustainable and intelligent world.,