4 Congestion Analysis Jobs

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10.0 - 12.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages...

Posted 1 week ago

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1.0 - 5.0 years

0 Lacs

vadodara, gujarat

On-site

As an individual responsible for modelling supply, demand, and grid congestion in US electricity markets for trading and long-term trend analysis, you will utilize power flow optimization and electrical engineering techniques to support trading decisions and system modeling, using tools such as Power World and PSSE. Conducting congestion analysis, outage distribution, and contingency analysis will also be part of your tasks. You will need to assess the impact of transmission upgrades and generation interconnections on grid congestion and market prices, as well as track electricity prices and effectively communicate market conditions to the trading team. To excel in this role, you are require...

Posted 1 month ago

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10.0 - 12.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages...

Posted 2 months ago

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7.0 - 11.0 years

0 Lacs

karnataka

On-site

As a Principal Physical Design Engineer focusing on New Product Development in Power Management at OnSemi in Bengaluru, India, you will play a crucial role in the development of Power management products for various applications such as consumer, industrial, and automotive sectors. Your responsibilities will include leading the P&R process, power planning, floor planning, clock tree building, congestion analysis for complex multi-power domain designs, and continuously seeking improvements in existing flows and methods to enhance Performance, Power, and Area (PPA) metrics. Your role will require strong problem-solving skills with a deep understanding of technical issues, allowing you to colla...

Posted 3 months ago

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